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hynix semiconductor 8-bit single-chip microcontrollers gms81508b gms82512 gms81516b gms82516 gms81524b gms81524 users manual (ver. 2.0)
version 2.0 published by mcu application team 2001 2001 2001 2001 hynix semiconductor inc. all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and repre- sentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. revision history ver 2.0 (this manual) may, 01, 2001 the manuals of gms81508b/16b/24b and gms82512/16/24 are integrated. choice-gang4 writer(for pc) is replaced with choice-gang4(for stand alone). ver 1.05 (before manual) sep., 20, 2000 choice-dr writer is omitted on the page 76 because it is not available any longer. for the hynix mcu on the all-07, writer program is only available from hynix sales part. please ask to hynix sales. hi-lo systems does not support the software of all-07 in their web site currently. ver 1.04 (before version) dec., 1999
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 1 table of contents 1. overview ...........................................1 description .........................................................1 features .............................................................1 development tools ............................................2 ordering information 2. block diagram ................................3 3. pin assignment ...............................5 4. package diagram ...........................8 5. pin function ...................................11 6. port structures .........................13 7. electrical characteristics ...15 absolute maximum ratings .............................15 recommended operating conditions ..............15 a/d converter characteristics .........................15 dc electrical characteristics ...........................16 ac characteristics ...........................................17 serial interface timing characteristics ............18 typical characteristic curves ..........................19 8. memory organization ................21 registers ..........................................................21 program memory .............................................24 data memory ...................................................27 addressing mode .............................................30 9. i/o ports ..........................................34 10. basic interval timer .................37 11. timer/event counter ...............39 8-bit timer / counter mode ..............................41 16-bit timer / counter mode ............................45 8-bit capture mode ..........................................46 16-bit capture mode ........................................47 12. analog digital converter .....49 13. serial communication .............51 transmission/receiving timing .......................53 the serial i/o operation by srdy pin ............ 53 the method of serial i/o ................................. 54 the method to test correct transmission ...... 54 14. pwm output .................................55 15. buzzer function ........................58 16. interrupts ...................................60 interrupt sequence .......................................... 62 brk interrupt .................................................. 63 multi interrupt .................................................. 64 external interrupt ............................................. 64 17. watchdog timer ........................67 18. power down operation ..........69 stop mode .................................................... 69 minimizing current consumption .................... 70 19. oscillator circuit ....................72 20. reset ..............................................73 external reset input ........................................ 73 watchdog timer reset ................................... 73 21. power fail processor ............74 22. otp programming ......................76 how to program .............................................. 76 pin function .................................................... 76 programming specification ............................. 80 a. control register list ................. i b. software example ...................... iii 7-segment led display .................................... iii c. instruction ...................................viii terminology list .............................................. viii instruction map ..................................................ix alphabetic order table of instruction ...................x instruction table by function ...........................xv d. mask order sheet ........................ xxi
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 1 gms81508b/16b/24b gms82512/16/24 cmos single-chip 8-bit microcontroller with a/d converter 1. overview 1.1 description the gms81508b/16b/24b are advanced cmos 8-bit microcontrollers with 8k/16k/24k bytes of rom and 64pin package. and the gms82512/16/24 are the same except for 12k/16k/24k bytes of rom and 42pin package. the gms825xx is a cut-down product of gms815xxb microcontroller, that is, the function and package are reduced. these are powerful micro- controllers which provide a highly flexible and cost effective solution to many general application. these includes several peripheral functions such as timer, a/d converter, programmable buzzer driver, serial i/o communication(gms815xxb only), pulse width modulation function( gms815xxb only), etc. the ram, rom, and i/o are placed on the same memory map in addition to simple instruction set. also, they support power saving mode to reduce power consumption. the gms815xxb is functionally 100% compatible with earier gms81508/16 or gms81508a/16a, and has better charac- teristics such as strong ems, wide operating voltage, temperature, frequency and fast programming time for the otp. 1.2 features ? 8k/16k/24k bytes on-chip program rom (12k/16k/24k bytes in gms825xx) ? 448 bytes of on-chip data ram (included stack memory) ? minimum instruction execution time 0.5 m m m m s at 8mhz ? one 8-bit basic interval timer ? four 8-bit timer/event counter or two 16-bit timer/event counter ? one 6-bit watchdog timer ? eight channel 8-bit a/d converter (four channel in gms825xx) ? two channel 8-bit pwm (not support in gms825xx) ? one 8-bit serial communication interface (not support in gms825xx) ? four external interrupt input ports ? buzzer driving port - 500hz ~ 250khz@8mhz ? 52 i/o ports, 4 input ports (35 i/o ports in gms825xx) ? twelve interrupt sources - basic interval timer: 1 - external input: 4 - timer/event counter: 4 - adc: 1 - serial interface: 1(not support in gms825xx) - wdt: 1 ? built in noise immunity circuit device name rom size ram size i/o otp package gms81508b 8k bytes 448 bytes 52 i/o, 4input gms81516bt 64sdip, 64mqfp, 64lqfp gms81516b 16k bytes 448 bytes 52 i/o, 4input gms81516bt gms81524b 24k bytes 448 bytes 52 i/o, 4input gms81524bt gms82512 12k bytes 448 bytes 35 i/o gms82524t 42sdip, 44mqfp gms82516 16k bytes 448 bytes 35 i/o gms82524t gms82524 24k bytes 448 bytes 35 i/o gms82524t
gms81508b/16b/24b, gms82512/16/24 2 may. 2001 ver 2.0 - noise filter - power fail processor ? power down mode - stop mode ? 2.2v to 5.5v wide operating range ? 1~10mhz wide operating frequency ? 64sdip, 64mqfp, 64lqfp package types (42sdip,44mqfp in gms825xx) ? available 16k, 24k bytes otp version (available 24k bytes in gms825xx) 1.3 development tools the gms815xxb and gms825xx are supported by a full- featured macro assembler, an in-circuit emulator choice-dr. tm and otp programmers. there are two different type programmers such as single type, gang type(stand-alone gang4). for more detail, refer to 22. otp programming on page 76. macro assembler operates under the ms-windows 95/98 tm . please contact sales part of hynix semiconductor. 1.4 ordering information device name rom size ram size package mask version gms81508b k gms81508b q gms81508b lq gms81516b k gms81516b q gms81516b lq gms81524b k gms81524b q gms81524b lq gms82512 k gms82512 q gms82516 k gms82516 q gms82524 k gms82524 q 8k bytes 8k bytes 8k bytes 16k bytes 16k bytes 16k bytes 24k bytes 24k bytes 24k bytes 12k bytes 12k bytes 16k bytes 16k bytes 24k bytes 24k bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 64sdip 64mqfp 64lqfp 64sdip 64mqfp 64lqfp 64sdip 64mqfp 64lqfp 42sdip 44mqfp 42sdip 44mqfp 42sdip 44mqfp otp version gms81516bt k gms81516bt q gms81516bt lq gms81524bt k gms81524bt q gms81524bt lq gms82524 k gms82524 q 16k bytes otp 16k bytes otp 16k bytes otp 24k bytes otp 24k bytes otp 24k bytes otp 24k bytes 24k bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 64sdip 64mqfp 64lqfp 64sdip 64mqfp 64lqfp 42sdip 44mqfp
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 3 2. block diagram 2.1 gms81508b/gms81516b/gms81524b(64 pin package) alu a interrupt controller data memory 8-bit adc 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watchdog timer pc r4 r5 r2 psw system controller timing generator system clock controller clock generator reset test x in x out r40 / int0 r41 / int1 r42 / int2 r43 / int3 r44 / ec0 r45 / ec2 r46 / t1o r47 / t3o r50 / sin r20~r27 v dd v ss power supply 8-bit serial r51 / sout r52 / sclk r53 / srdy r54 / wdto r55 / buz r56 / pwm0 r57 / pwm1 r1 r10~r17 r0 r00~r07 r3 r30~r37 interface buzzer driver r6 r60 / an0 r61 / an1 r62 / an2 r63 / an3 r64 / an4 r65 / an5 r66 / an6 r67 / an7 (448 bytes) 8-bit pwm av dd av ss adc power supply stack pointer x y
gms81508b/16b/24b, gms82512/16/24 4 may. 2001 ver 2.0 2.2 gms82512/gms82516/gms82524(42 pin package) alu a interrupt controller data memory 8-bit adc 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watchdog timer pc r4 r5 r0 psw system controller timing generator system clock controller clock generator reset test x in x out r40 / int0 r41 / int1 r42 / int2 r43 / int3 r44 / ec0 r00~r07 v dd v ss power supply r54 / wdto r55 / buz r2 r20~r27 buzzer driver r6 r64 / an4 r65 / an5 r66 / an6 r67 / an7 (448 bytes) av dd adc power supply stack pointer x y r3 r30~r37
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 5 3. pin assignment 3.1 gms81508b/gms81516b/gms81524b(64 pin package) v dd test av ss av dd r67 r66 r65 r64 r63 r62 r61 r60 r57 r56 r55 r54 an7 an6 an5 an4 an3 an2 an1 an0 pwm1 pwm0 buz wdto r53 r52 r51 r50 r47 r46 r45 r44 r43 r42 r41 r40 reset xin xout v ss srdy sclk sout sin t3o t1o ec2 ec0 int3 int2 int1 int0 r30 r31 r32 r33 r34 r35 r36 r37 r00 r01 r02 r03 r04 r05 r06 r07 r10 r11 r12 r13 r14 r15 r16 r17 r20 r21 r22 r23 r24 r25 r26 r27 r66 r36 r35 r34 r33 r32 r31 r30 v dd test av ss av dd r67 an6 an7 r42 r22 r23 r24 r25 r26 r27 v ss xout xin reset r40 r41 int2 int0 int1 r37 r01 r02 r03 r04 r05 r06 r07 r10 r11 r12 r13 r14 r15 r16 r17 r00 r20 r21 r65 r63 r62 r61 r60 r57 r56 r55 r54 r53 r52 r51 r50 r47 r46 r45 r64 r44 r43 an5 an3 an2 an1 an0 pwm1 pwm0 buz wdto srdy sclk sout sin t3o t1o ec2 an4 ec0 int3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 64mqfp 64sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gms81508b/16b/24b gms81508b/16b/24b (top view) (top view)
gms81508b/16b/24b, gms82512/16/24 6 may. 2001 ver 2.0 r20 r21 r22 r23 r24 r25 r26 r27 v ss xout xin reset r40 r41 r42 r43 r00 r01 r02 r03 r04 r05 r06 r07 r10 r11 r12 r13 r14 r15 r16 r17 r63 r62 r61 r60 r57 r56 r55 r54 r53 r52 r51 r50 r47 r46 r45 r44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r37 r36 r35 r34 r33 r32 r31 r30 v dd test av ss av dd r67 r66 r65 r64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 gms81508b/16b/24b 64lqfp an3 an2 an1 an0 pwm1 pwm0 buz wdto srdy sclk sout sin t3o t1o ec2 ec0 int2 int0 int1 int3 an5 an7 an6 an4 (top view)
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 7 3.2 gms82512/gms82516/gms82524(42 pin package) r30 v dd test av dd r67 r66 r65 r64 r55 r54 r44 r43 r42 r41 r40 reset an7 an6 an5 an4 buz wdto ec0 int3 int2 int1 int0 xin xout v ss r27 r26 r31 r32 r33 r34 r35 r36 r37 r00 r01 r02 r03 r04 r05 r06 r07 r20 r21 r22 r23 r24 r25 42sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 gms82512/16/24 (top view) (top view) r21 r22 r23 r24 r25 r26 r27 v ss xout xin reset r37 r00 r01 r02 r03 r04 r05 r06 r07 n.c. * r20 r66 r65 r64 n.c. * r55 r54 r44 r43 r42 r41 r40 1 2 3 4 5 6 7 8 9 10 11 r36 r35 r34 r33 r32 r31 r30 v dd test av dd r67 33 32 31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 gms82512/16/24 44mqfp an6 an5 an4 buz wdto ec0 int3 int2 int1 int0 an7 18 19 20 21 22 n.c. * : no connection
gms81508b/16b/24b, gms82512/16/24 8 may. 2001 ver 2.0 4. package diagram 4.1 gms81508b/gms81516b/gms81524b(64 pin package) unit: inch 2.280 2.260 0.022 0.016 0.050 0.030 0.070 typ. 0.140 0.120 min. 0.015 0.680 0.660 0.750 typ. 0-15 64sdip 0 .01 2 0.00 8 0.205 max. 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35 1.00 typ. see detail a 1.03 0.73 0-7 0.36 0.10 0.23 0.13 1.95 ref detail a unit: mm 64mqfp
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 9 1.60 max. see detail a 0.75 0.45 0-7 0.15 0.05 1.00 ref detail a unit: mm 10.00 typ. 12.00 typ. 12.00 typ. 10.00 typ. 0.38 0.22 0.50 typ. 1.45 1.35 64lqfp
gms81508b/16b/24b, gms82512/16/24 10 may. 2001 ver 2.0 4.2 gms82512/gms82516/gms82524(42 pin package) 44mqfp 2.35 max. see detail a 1.03 0.73 0-7 0.25 0.10 1.60 typ. detail a unit: mm 0.45 0.30 0.80 typ. 2.10 1.95 0.23 0.13 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95 unit: inch 1.465 1.455 0.022 0.016 0.045 0.035 0.070 typ. 0.140 0.120 min. 0.015 0.545 0.535 0.600 typ. 0-15 42sdip 0 .0 1 2 0 .0 08 0.190 max.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 11 5. pin function v dd : supply voltage. v ss : circuit ground. test : used for test mode. for normal operation, it should be connected to v dd . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r10~r17 : r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. these pins are not served on gms825xx. r20~r27 : r2 is an 8-bit cmos bidirectional i/o port. r2 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r30~r37 : r3 is an 8-bit cmos bidirectional i/o port. r3 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r40~r47 : r4 is an 8-bit cmos bidirectional i/o port. r4 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r45, r46, r47 are not served on gms825xx. in addition, r4 serves the functions of the various follow- ing special features. r50~r57 : r5 is an 8-bit cmos bidirectional i/o port. r5 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r50~r53, r56, r57 are not served on gms825xx. in addition, r5 serves the functions of the various follow- ing special features. r60~r67 : r6 is an 8-bit cmos bidirectional i/o port. r6 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r60~r63 are not served on gms825xx. in addition, r6 is shared with the adc input. note: on the mds(choice-dr, jr), when the mcu is re- set, r60 can not be used digital input port. for more detail, refer to "9. i/o ports" on page 34. av dd : supply voltage to the ladder resistor of adc cir- cuit. to enhance the resolution of analog to digital convert- er, use independent power source as well as possible, other than digital power source. av ss : adc circuit ground. av ss is not served on gms825xx but it is connected to v ss internally. port pin alternate function r40 r41 r42 r43 r44 r45 r46 r47 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) int3 (external interrupt 3) ec0 (event counter input 0) ec2 (event counter input 2) t1o (timer/counter 1 output) t3o (timer/counter 3 output) port pin alternate function r50 r51 r52 r53 r54 r55 r56 r57 sin (serial data input) sout (serial data output) sclk (serial clock) srdy (serial ready) wdto (watchdog timer output) buz (buzzer driver output) pwm0 (pwm output 0) pwm1 (pwm output 1) port pin alternate function r60 r61 r62 r63 r64 r66 r66 r67 an0 (analog input 0) an1 (analog input 1) an2 (analog input 2) an3 (analog input 3) an4 (analog input 4) an5 (analog input 5) an6 (analog input 6) an7 (analog input 7)
gms81508b/16b/24b, gms82512/16/24 12 may. 2001 ver 2.0 * this pins are not served on gms825xx. 1. the parenthesis means alternate function. pin name in/out function basic alternate v dd - supply voltage v ss - circuit ground test i controls test mode of the chip, for normal operation, it should be connected at v dd . reset i reset signal input x in i oscillation input x out o oscillation output r00~r07 i/o 8-bit general i/o ports * r10~r17 i/o 8-bit general i/o ports r20~r27 i/o 8-bit general i/o ports r30~r37 i/o 8-bit general i/o ports r40 (int0) i/o (i) 8-bit general i/o ports external interrupt 0 input r41 (int1) i/o (i) external interrupt 1 input r42 (int2) i/o (i) external interrupt 2 input r43 (int3) i/o (i) external interrupt 3 input r44 (ec0 ) i/o (i) timer/counter 0 external input * r45 (ec2 ) i/o (i) timer/counter 2 external input * r46 (t1o) i/o (o) timer/counter 1 output * r47 (t3o) i/o (o) timer/counter 3 output * r50 (sin) i/o (i) 8-bit general i/o ports serial data input * r51 (sout) i/o (o) serial data output * r52 (sclk) i/o (i/o) serial clock i/o * r53 (srdy ) i/o (i/o) receive enable i/o r54 (wdto) i/o (o) watchdog timer overflow output r55 (buz) i/o (o) buzzer driving output * r56 (pwm0) i/o (o) pwm pulse output * r57 (pwm1) i/o (o) * r60~r63 (an0~an3) i (i) general input ports analog voltage input r64~r67 (an4~an7) i/o (i) general i/o ports * av ss - ground level input pin for adc av dd - supply voltage input pin for adc table 5-1 port function description
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 13 6. port structures r00~r07, r10~r17, r20~r27, r30~37 r40/int0, r41/int1, r42/int2, r43/int3, r44/ ec0 , r45/ec2 , r50/sin r46/t1o, r47/t3o, r51/sout, r54/wdto r55/buz, r56/pwm0, r57/pwm1 r52/sclk s53/srdy pin data reg. dir. rd v dd vss reg. data bus mux mux data bus v dd v ss pin data reg. direction reg. rd pmr selection alternate function ex) int0 mux data bus v dd v ss pin data reg. direction reg. rd mux selection secondary function mux data bus v dd v ss pin data reg. direction reg. rd mux selection sck output mux sck input exck mux data bus v dd v ss pin data reg. direction reg. rd mux selection srdy output srdy input srdy
gms81508b/16b/24b, gms82512/16/24 14 may. 2001 ver 2.0 r60/an0 ~ r63/an3 r64/an7 ~ r67/an7 x in , x out reset test v dd v ss rd to a/d converter data bus pin data reg. dir. rd v dd v ss reg. data bus mux to a/d converter xin v dd v ss xout v ss stop reset v dd v ss test v dd v ss otp version: disconnected mask version: connected
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 15 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ............................................. -0.3 to +7.0 v storage temperature .................................. -40 to +125 c voltage on any pin with respect to ground (v ss ) ..................................................................-0.3 to v dd +0.3 maximum current out of v ss pin .......................... 150 ma maximum current into v dd pin .............................. 80 ma maximum current sunk by (i ol per i/o pin) .......... 20 ma maximum output current sourced by (i oh per i/o pin) ................................................................................... 8 ma maximum current ( s i ol ) ...................................... 100 ma maximum current ( s i oh )........................................ 50 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 a/d converter characteristics (t a =25 c, v ss =0v, v dd =av dd =5.12v@f xin =8mhz, v dd =av dd =3.072v@f xin =4mhz) parameter symbol condition specifications unit min. max. supply voltage v dd f xin =1 ~ 10 mhz f xin =1 ~ 8 mhz f xin =1 ~ 4 mhz 4.5 2.7 2.2 5.5 5.5 5.5 v operating frequency f xin v dd =4.5~5.5v v dd =2.7~5.5v v dd =2.2~5.5v 1 1 1 10 8 4 mhz operating temperature t opr normal version temperature extention version -20 -40 85 85 c parameter symbol specifications unit min. typ. 1 max. f xin =4mhz f xin =8mhz analog input voltage range v ain v ss - av dd av dd v non-linearity error n nle - 1.0 1.5 1.5 lsb differential non-linearity error n dnle - 1.0 1.5 1.5 lsb zero offset error n zoe - 0.5 1.5 1.5 lsb full scale error n fse - 0.35 0.5 0.5 lsb gain error n ge - 1.0 1.5 1.5 lsb overall accuracy n acc - 1.0 1.5 1.5 lsb av dd input current i ref -0.51.01.0 ma conversion time t conv --4020 m s
gms81508b/16b/24b, gms82512/16/24 16 may. 2001 ver 2.0 7.4 dc electrical characteristics (t a =-20~85 c, v dd =2.7~5.5v, ta= -20~85 c, f xin =8mhz, v ss =0v) , analog power supply input range av dd 0.9v dd v dd 1.1v dd v 1. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter symbol condition specifications unit min. typ. 1 1. data in typ. column is at 4.5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max. input high voltage v ih1 v dd =4.5 v dd =2.7 x in , reset , r4, r5, r6 0.8v dd - v dd +0.3 v v ih2 r0, r1, r2, r3 0.7v dd - v dd +0.3 input low voltage v il1 v dd =4.5 v dd =2.7 x in , reset , r4, r5, r6 - 0.2v dd v v il2 r0, r1, r2, r3 - 0.3v dd output high voltage v oh v dd =4.5 v dd =2.7 i oh1 =-2ma r0,r1,r2,r3,r4,r5 r6 v dd -1.0 --v output low voltage v ol v dd =4.5 v dd =2.7 i ol1 =5ma r0,r1,r2,r3,r4,r5 r6 - -1.0v power fail detect voltage v pfd v pfd =3.0v v pfd =2.4v @ t a =25 c0.9v pfd 1.1v pfd v input high leakage current i ih1 v in =v dd all input pins -5.0 - 5.0 m a input low leakage current i il v in =v ss all input pins -5.0 - 5.0 m a hysteresis v t+ , v t- reset , ec0 , ec2 , sin, sclk, int0~int3 0.3 0.8 v power current i dd1 f xin =8mhz all input = v ss crystal oscillator, c l1 =c l2 =30pf -820ma i dd2 f xin =4mhz 410ma i stop all input = v ss -110 m a parameter symbol specifications unit min. typ. 1 max. f xin =4mhz f xin =8mhz
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 17 7.5 ac characteristics (t a =-20~+85 c, v dd =5v 10%, v ss =0v) figure 7-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f xin x in 1.0 - 10.0 mhz oscillation stabilizing time t st x in , x out - - 20 ms external clock pulse width t cpw x in 40 - - ns external clock transi- tion time t rcp, t fcp x in --20ns interrupt pulse width t iw int0, int1, int2, int3 2 - - t sys reset input width t rst reset 8- - t sys event counter input pulse width t ecw ec0 , ec2 2- - t sys event counter transi- tion time t rec, t fec ec0 , ec2 --20ns t rcp t fcp xin int0~int3 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset t rec t fec 0.2v dd 0.8v dd ec0 , ec2 t iw t iw t rst t ecw t ecw t sys = 1/f xin t cpw t cpw
gms81508b/16b/24b, gms82512/16/24 18 may. 2001 ver 2.0 7.6 serial interface timing characteristics (t a =-20~+85 c, v dd =5v 10%, v ss =0v, f xin =8mhz) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. serial input clock pulse t scyc sclk 2t sys +200 -8ns serial input clock pulse width t sckw sclk t sys +70 -8ns serial input clock pulse transition time t fsck t rsck sclk - - 30 ns sin input pulse transition time t fsin t rsin sin - - 30 ns sin input setup time (external sclk) t sus sin 100 - - ns sin input setup time (internal sclk) t sus sin 200 - ns sin input hold time t hs sin t sys +70 -ns serial output clock cycle time t scyc sclk 4t sys - 16t sys ns serial output clock pulse width t sckw sclk t sys -30 ns serial output clock pulse transition time t fsck t rsck sclk 30 ns serial output delay time s out sout 100 ns sclk sin 0.2v dd sout 0.2v dd 0.8v dd t scyc t sckw t sckw t rsck t fsck 0.8v dd t sus t hs t ds 0.2v dd 0.8v dd t rsin t fsin
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 19 7.7 typical characteristic curves this graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) ta=25 c 1 f xin =8mhz ta=25 c f xin =8mhz xin, reset , r0, r1, r2, r3 pins i oh - v oh -12 -9 -6 -3 0 0.3 0.6 0.9 1.2 1.5 (v) ta=25 c v dd =4.5v r0~r6 pins (ma) i oh v dd -v oh i ol - v ol1 20 15 10 5 0 (ma) i ol 0.2 0.4 0.6 0.8 1.0 v ol (v) ta=25 c v dd =4.5v r0~r6 pins i oh - v oh -12 -9 -6 -3 0 0.3 0.6 0.9 1.2 1.5 (v) ta=25 c v dd =3.0v r0~r6 pins (ma) i oh v dd -v oh i ol - v ol2 20 15 10 5 0 (ma) i ol 0.2 0.4 0.6 0.8 1.0 v ol (v) ta=25 c v dd =3.0v r0~r6 pins r4, r5, r6 pins
gms81508b/16b/24b, gms82512/16/24 20 may. 2001 ver 2.0 ta= -20~85 c ta=25 c i dd - v dd 20 15 10 5 0 (ma) i dd 23 45 6 v dd (v) normal operation 10 6 4 2 0 (mhz) f xin 23 45 6 v dd (v) operating area i stop - v dd 0.4 0.3 0.2 0.1 0 ( m a) i dd 23 45 6 v dd (v) stop mode 85 c 25 c -20 c f xin = 8mhz 4mhz v dd - v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) v dd - v il1 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) ta=25 c 1 f xin =8mhz ta=25 c f xin =8mhz r0, r1, r2, r3 pins 8 xin, reset , r4, r5, r6 pins
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 21 8. memory organization the gms81508b/16b/24b and gms82512/16/24 have separate address spaces for program memory and data memory. program memory can only be read, not written to. it can be up to 24k bytes of program memory. data memory can be read and written to up to 448 bytes includ- ing the stack area. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 100 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. normally, the initial value of fe h is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0feh txsp ; sp ? feh address 01ff h can not be used as stack. don not use 1ff h , or malfunction would be occurred. program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. accumulator x register y register stack pointer program counter program status word x a sp y pcl psw pch two 8-bit registers can be used as a ya 16-bit register y a y a sp 01 h stack address (100 h ~ 1fe h ) bit 15 bit 0 87 hardware fixed 00 h ~fe h
gms81508b/16b/24b, gms82512/16/24 22 may. 2001 ver 2.0 [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned 100 h to 1ff h . it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value: 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is selected to page 1
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 23 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01fb sp after execution sp before execution 01fc 01fc 01fd 01fe 01fe push down at acceptance of interrupt pcl pch 01fb 01fb 01fc 01fd 01fe 01fe push down psw at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fc pop up at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fb pop up psw 0100h 01feh stack depth at execution of push instruction a 01fb 01fd 01fc 01fd 01fe 01fe push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01fb 01fe 01fc 01fd 01fe 01fd pop up pop a (x,y,psw)
gms81508b/16b/24b, gms82512/16/24 24 may. 2001 ver 2.0 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 24k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5, shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each area is assigned a fixed loca- tion in program memory. program memory area contains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area interrupt vector area d000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area e000 h c000 h tcall area gms81508b, 8k rom gms81516b/gms82516, 16k rom gms81524b/gms82524, 24k rom gms82512, 12k rom a000 h ~ ~ ~ ~ 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - * serial communication interface basic interval timer - - - external interrupt 2 timer/counter 1 interrupt external interrupt 0 - reset vector area external interrupt 1 watchdog timer interrupt - means reserved area. note: timer/counter 2 interrupt external interrupt 3 timer/counter 0 interrupt timer/counter 3 interrupt a/d converter * is not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 25 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: fh fh dh 6h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h t ? 0d125 h reverse
gms81508b/16b/24b, gms82512/16/24 26 may. 2001 ver 2.0 example: the usage software example of vector address for gms81524b. org 0ffe0h dw not_used dw not_used dw sio ; serial interface dw bit_timer ; basic interval timer dw wd_timer ; watchdog timer dw adc ; adc dw timer3 ; timer-3 dw timer2 ; timer-2 dw timer1 ; timer-1 dw timer0 ; timer-0 dw int3 ; int.3 dw int2 ; int.2 dw int1 ; int.1 dw int0 ; int.0 dw not_used ; - dw reset ; reset org 0a000h ; 24k rom start address ; org 0c000h ; 16k rom start address ; org 0d000h ; 12k rom start address ; org 0e000h ; 8k rom start address ;******************************************* ; main program * ;******************************************* ; reset: di ;disable all interrupts clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0feh ;stack pointer initialize txsp ; ldm r0, #0 ;normal port 0 ldm r0dd,#82h ;normal port direction : : : ldm tdr0,#250 ;8us x 250 = 2000us ldm tm0,#1fh ;start timer0, 8us at 8mhz ldm irqh,#0 ldm irql,#0 ldm ienh,#0c8h ;enable timer0, int0, int1 ldm ienl,#0 ldm ieds,#55h ;select falling edge detect on int pin ldm pmr4,#3h ;set external interrupt pin(int0, int1) ei ;enable master interrupt : : : : : not_used:nop reti
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 27 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into four groups, a user ram, control registers, stack, and lcd memory. figure 8-8 data memory map user memory the gms815xxb and gms825xx have 448 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore, these registers contain control and sta- tus bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction, for example ldm. example; to write at ckctlr ldm clctlr,#09h ;divide ratio( ? 32) stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 23. user memory control registers or stack area 0000 h 00bf h 00c0 h 00ff h 0100 h 01ff h page0 user memory page1 when g-flag=0, when g-flag=1 this page is selected
gms81508b/16b/24b, gms82512/16/24 28 may. 2001 ver 2.0 address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w undefined page 34 00c1 r0 port i/o direction register r0dd w 0 0 0 0 0 0 0 0 page 34 * 00c2 r1 port data register r1 r/w undefined page 34 * 00c3 r1 port i/o direction register r1dd w 0 0 0 0 0 0 0 0 page 34 00c4 r2 port data register r2 r/w undefined page 34 00c5 r2 port i/o direction register r2dd w 0 0 0 0 0 0 0 0 page 34 00c6 r3 port data register r3 r/w undefined page 34 00c7 r3 port i/o direction register r3dd w 0 0 0 0 0 0 0 0 page 34 00c8 r4 port data register r4 r/w undefined page 34 00c9 r4 port i/o direction register r4dd w 0 0 0 0 0 0 0 0 page 34 00ca r5 port data register r5 r/w undefined page 34 00cb r5 port i/o direction register r5dd w 0 0 0 0 0 0 0 0 page 34 00cc r6 port data register r6 r/w undefined page 34 00cd r6 port i/o direction register r6dd w 0 0 0 0 - - - - page 34 00d0 r4 port mode register pmr4 w 0 0 0 0 0 0 0 0 page 34, page 66 00d1 r5 port mode register pmr5 w - - 0 0 - - - - page 34, page 58 00d3 basic interval timer mode register bitr r undefined page 37 clock control register ckctlr w - - 0 1 0 1 1 1 page 37 00e0 watchdog timer register wdtr w - 0 1 1 1 1 1 1 page 67 00e2 timer mode register 0 tm0 r/w 0 0 0 0 0 0 0 0 page 39 00e3 timer mode register 2 tm2 r/w 0 0 0 0 0 0 0 0 page 39 00e4 timer 0 data register tdr0 w undefined page 39 timer 0 counter register t0 r undefined page 39 00e5 timer 1 data register tdr1 w undefined page 39 timer 1 counter register t1 r undefined page 39 00e6 timer 2 data register tdr2 w undefined page 39 timer 2 counter register t2 r undefined page 39 00e7 timer 3 data register tdr3 w undefined page 39 timer 3 counter register t3 r undefined page 39 00e8 a/d converter mode register adcm r/w - - 0 0 0 0 0 1 page 49 00e9 a/d converter data register adr r undefined page 49 * 00ea serial i/o mode register siom r/w - 0 0 0 0 0 0 1 page 51 * 00eb serial i/o register sior r/w undefined page 51 00ec buzzer driver register bur w undefined page 58 table 8-1 control registers
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 29 * 00f0 pwm0 duty register pwmr0 w undefined page 55 * 00f1 pwm1 duty register pwmr1 w undefined page 55 * 00f2 pwm control register pwmcr w 0 0 0 0 0 0 0 0 page 55 00f4 interrupt enable register low ienl r/w 0 0 0 0 - - - - page 60 00f5 interrupt request flag register low irql r/w 0 0 0 0 - - - - page 60 00f6 interrupt enable register high ienh r/w 0 0 0 0 0 0 0 0 page 60 00f7 interrupt request flag register high irqh r/w 0 0 0 0 0 0 0 0 page 60 00f8 external interrupt edge selection register ieds w 0 0 0 0 0 0 0 0 page 60 00f9 power fail detection register pfdr r/w - - - - 1 1 0 0 page 74 address register name symbol r/w initial value page 76543210 table 8-1 control registers registers are controlled by byte manipulation instruction such as ldm etc., do not use bit manipulation w registers are controlled by both bit and byte manipulation instruction. r/w instruction such as set1, clr1 etc. if bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved. * : this bit is not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 30 may. 2001 ver 2.0 8.4 addressing mode the gms800 series mcu uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1 e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35h ;a ? ram[35h] 35 a+35h+c ? a 04 memory e4 0f100h data 55h ~ ~ ~ ~ data 0135h t 35 0f102h 55 0f101h data 35 35h 0e551h data ? a t ~ ~ ~ ~ c5 0e550h
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 31 (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag. 983501 inc !0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1 d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h 07 0f100h ~ ~ ~ ~ data 0f035h t f0 0f102h 35 0f101h a+data+c ? a address: 0f035 98 0f100h ~ ~ ~ ~ data 135h t 01 0f102h 35 0f101h data+1 ? data ? address: 0135 data d4 115h 0e550h data ? a t ~ ~ ~ ~ data db 35h data ? a t ~ ~ ~ ~ 36h ? x
gms81508b/16b/24b, gms82512/16/24 32 may. 2001 ver 2.0 c645 lda 45h+x y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory.this addressing mode can specify memo- ry in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] y indexed indirect ? ? ? ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h data 45 3ah 0e551h data ? a t ~ ~ ~ ~ c6 0e550h 45h+0f5h=13ah ? d5 0f100h data ? a t ~ ~ ~ ~ data 0fa55h 0fa00h+55h=0fa55h ? fa 0f102h 00 0f101h 0a 35h jump to t ~ ~ ~ ~ 35 0fa00h e3 36h 3f 0e30ah next ~ ~ ~ ~ address 0e30ah 05 35h 0e005h ~ ~ ~ ~ 25 0fa00h e0 36h 16 0e005h data ~ ~ ~ ~ ? a + data + c ? a 25 + x(10) = 35 h t
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 33 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 1f25e0 jmp [!0c025h] 05 25h 0e005h + y(10) t ~ ~ ~ ~ 25 0fa00h e0 26h 17 0e015h data ~ ~ ~ ~ ? = 0e015h a + data + c ? a 25 0e025h jump to ~ ~ ~ ~ e0 0fa00h e7 0e026h 25 0e725h next ~ ~ ~ ~ 1f program memory t address 0e30ah
gms81508b/16b/24b, gms82512/16/24 34 may. 2001 ver 2.0 9. i/o ports the gms815xxb and gms825xx have four input ports and fifty two input/output ports(r00~r67) and the gms825xx has thirty five input/output ports. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. all pins have data direction registers which can define these ports as output or input. a 1 in the port direction register configure the corresponding port pin as output. conversely, write 0 to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write 55 h to address 0c1 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1. all the port direction registers in the gms815xxb and gms825xx have 0 written to them by reset function. on the other hand, its initial status is input. figure 9-1 example of port i/o assignment r0 and r0dd register: r0 is an 8-bit cmos bidirection- al i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c1 h ). r1 and r1dd register: r1 is an 8-bit cmos bidirection- al i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c3 h ). r10~r17 are not served on gms825xx. r2 and r2dd register: r2 is an 8-bit cmos bidirection- al i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 0c5 h ). i: input port write 55 h to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r1 data r0 direction r1 direction 0c0 h 0c1 h 0c2 h 0c3 h 76543210 bit 76543210 port o: output port r0 data register r0 address: 0c0 h reset value: undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0dd address: 0c1 h reset value: 00 h 0: input 1: output input / output data r1 data register r1 address: 0c2 h reset value: undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r1 direction register r1dd address: 0c3 h reset value: 00 h 0: input 1: output input / output data r2 data register r2 address: 0c4 h reset value: undefined r27 r26 r25 r24 r23 r22 r21 r20 port direction r2 direction register r2dd address: 0c5 h reset value: 00 h 0: input 1: output input / output data
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 35 r3 and r3dd register: r3 is an 8-bit cmos bidirection- al i/o port (address 0c6 h ). each i/o pin can independently used as an input or an output through the r3dd register (address 0c7 h ). r4 and r4dd register: r4 is an 8-bit cmos bidirection- al i/o port (address 0c8 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0c9 h ). in addition, port r4 is multiplexed with various special features. the control register pmr4 (address 0d0 h ) con- trols the selection of alternate function. after reset, this value is 0, port may be used as normal i/o port. to use alternate function such as external interrupt, exter- nal counter input or timer clock out, write 1 in the corre- sponding bit of pmr4. r45~r47 are not served on gms825xx. regardless of the direction register r4dd, pmr4 is select- ed to use as alternate functions, port pin can be used as a corresponding alternate features. port pin alternate function r40 r41 r42 r43 r44 r45 r46 r47 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) int3 (external interrupt 3) ec0 (external count input to timer/ counter 0) ec2 (external count input to timer/ counter 2) t1o (timer 1 clock-out) t3o (timer 3 clock-out) r3 data register r3 address: 0c6 h reset value: undefined r37 r36 r35 r34 r33 r32 r31 r30 port direction r3 direction register r3dd address: 0c7 h reset value: 00 h 0: input 1: output input / output data r4 port mode register pmr4 address: 0d0 h reset value: 00 h 0: r40 1: int0 0 0: r41 1: int1 0: r42 1: int2 0: r43 1: int3 0: r44 1: ec0 0: r45 1: ec2 0: r46 1: t1o 0: r47 1: t3o 1 2 3 4 5 6 7 edge selection register ieds address: 0f8h reset value: 00h 0 1 2 3 4 5 6 7 int0 int1 int2 int3 external interrupt edge select 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) r4 data register r4 address: 0c8 h reset value: undefined r47 r46 r45 r44 r43 r42 r41 r40 port direction r4 direction register r4dd address: 0c9 h reset value: 00 h 0: input 1: output input / output data
gms81508b/16b/24b, gms82512/16/24 36 may. 2001 ver 2.0 r5 and r5dd register: r5 is an 8-bit cmos bidirection- al i/o port (address 0ca h ). each i/o pin can independent- ly used as an input or an output through the r5dd register (address 0cb h ). the control register pmr5 (address d1 h ) controls the se- lection alternate function. after reset, this value is 0, port may be used as general i/o ports. to use buzzer function, write 1 to the pmr5 and the pin r55 must be defined as output mode (the bit 5 of r5dd=1). also, port r5 can be used to alternate function by si- om(address 0eah) and pwmcr(0f2h). r50~r53, r56 and r57 are not served on gms825xx. r6 and r6dd register: r6 is an 8-bit cmos bidirection- al i/o port (address 0cc h ). each i/o pin can independent- ly used as an input or an output through the r6dd register (address 0cd h ). r60~r63 are not served on gms825xx. r6dd (address cd h ) controls the direction of the r6 pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. note: on the mds(choice-dr,jr), when the mcu is re- set, r60 can not be used digital input port, because this port is selected as an analog input port by adcm register. to use this port as a digital i/o port, change the value of lower 4 bits of adcm (address 0e8 h ). on the other hand, r6 port, all eight pins can not be used as digital i/o port si- multaneously on the mds. at least one pin is used as an analog input. but on the otp and main chip, r6 port, all eight pins can be used as digital i/o port at the same time. port pin alternate function r50 r51 r52 r53 r54 r55 r56 r57 sin(serial data input) sout(serial data output) sclk(serial clock) srdy (ready signal) wdto (watchdog timer output) buz (square-wave output for buzzer) pwm0 pwm1 r5 port mode register pmr5 address: 0d1 h reset value: --00---- b - - - - r54/wdto selection buz - - 0: r54 1: wdto (output) r55/buz selection 0: r55 1: buz (output) wdto r5 data register r5 address: 0ca h reset value: undefined r57 r56 r55 r54 r53 r52 r51 r50 port direction r5 direction register r5dd address: 0cb h reset value: 00 h 0: input 1: output input / output data port pin alternate function r60 r61 r62 r63 r64 r65 r66 r67 an0 (adc input 0) an1 (adc input 1) an2 (adc input 2) an3 (adc input 3) an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) r6 data register r6 address: 0cc h reset value: undefined r67 r66 r65 r64 r63 r62 r61 r60 port direction r6 direction register r6dd address: 0cd h reset value: 0000---- b 0: input 1: output input / output data ---- r60~r63 are input input data only
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 37 10. basic interval timer the gms815xxb and gms825xx have one 8-bit basic in- terval timer that is free-run and can not stop. block dia- gram is shown in figure 10-1. in addition, the basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (bitif). as the count overflow from ff h to 00 h , this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 10-2. source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and ad- dress 0f9 h is read as a bitr, and written to ckctlr. figure 10-1 block diagram of basic interval timer table 10-1 basic interval timer interrupt time mux basic interval timer interrupt bitr select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl ? 2048 ? 1024 ? 512 ? 256 ? 128 ? 64 ? 32 ? 16 to watchdog timer (wdtck) ckctlr clear overflow internal bus line clock control register [0d3 h ] [0f9 h ] bitif read x in pin prescaler ckctlr [2:0] source clock interrupt (overflow) period (ms) @ f xin = 8mhz 000 001 010 011 100 101 110 111 f xin ? 16 f xin ? 32 f xin ? 64 f xin ? 128 f xin ? 256 f xin ? 512 f xin ? 1024 f xin ? 2048 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536
gms81508b/16b/24b, gms82512/16/24 38 may. 2001 ver 2.0 figure 10-2 bitr: basic interval timer mode register example 1: interrupt request flag is generated every 8.192ms at 4mhz. : ldm ckctlr,#1bh set1 bite ei : example 2: interrupt request flag is generated every 8.192ms at 8mhz. : ldm ckctlr,#1ch set1 bite ei : btcl 76543210 wdton - - bts1 basic interval timer source clock select 000: f xin ? 16 001: f xin ? 32 010: f xin ? 64 011: f xin ? 128 100: f xin ? 256 101: f xin ? 512 110: f xin ? 1024 111: f xin ? 2048 clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to 0. this bit becomes 0 automatically initial value: --01 0111 b address: 0d3 h after one machine cycle, and starts counting. ckctlr initial value: undefined address: 0d3 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter enpck bts0 bts2 btcl btcl 76543210 enable peripheral clock if this bit is 0, all peripherals are disabled such as timer, adc, pwm, etc. 0: operate as a 6-bit general timer 1: enable watchdog timer operation see the section watchdog timer.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 39 11. timer/event counter the gms815xxb and gms825xx have four timer/ counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 are can be used either two 8-bit tim- er/counter or one 16-bit timer/counter with combine them. also timer 2 and timer 3 are same. in the timer function, the register is increased every in- ternal clock input. thus, one can think of it as counting in- ternal clock input. since a least clock consists of 4 and most clock consists of 64 oscillator periods, the count rate is 1/4 to 1/64 of the oscillator frequency. in the counter function, the register is incremented in re- sponse to a 1-to-0 (in case of falling edge) transition at its corresponding external input pin, ec0 or ec2 . (ec2 are not served on gms825xx.) in addition the capture function, the register is incre- mented in response external or internal clock sources same with timer or counter function. when external clock edge input, the count register is captured into timer data register correspondingly. it has four operating modes: 8-bit timer/counter, 16-bit timer/counter, 8-bit capture, 16-bit capture which are selected by bit in timer mode register tm0 and tm2 as shown in table 11-1. in operation of timer 2, timer 3, their operations are same with timer 0, timer 1, respectively as shown in table 11- 2. ec0 , ec2 , t1o(timer 3 rectangular pulse output) and t3o are determined by pmr4. tm0 timer 0 timer 1 cap 0 t1st t1sl [1:0] t0st t0cn t0sl[1:0] 0x 01 or 10 or 11 x x 01 or 10 or 11 8-bit timer 8-bit timer 0 x x x 00 8-bit event counter 8-bit timer 1 x x x 01 or 10 or 11 8-bit capture (internal clock) 8-bit timer 1 x x x 00 8-bit capture (external clock) 8-bit timer 0x 00 x x 01 or 10 or 11 16-bit timer 0 x x x 00 16-bit event counter 1 x x x 01 or 10 or 11 16-bit capture (internal clock) 1 x x x 00 16-bit capture (external clock) table 11-1 tm0 timer mode register tm2 timer 2 timer 3 cap 2 t3st t3sl [1:0] t2st t2cn t2sl[1:0] 0x 01 or 10 or 11 x x 01 or 10 or 11 8-bit timer 8-bit timer 0 x x x 00 8-bit event counter 8-bit timer 1 x x x 01 or 10 or 11 8-bit capture (internal clock) 8-bit timer 1 x x x 00 8-bit capture (external clock) 8-bit timer 0x 00 x x 01 or 10 or 11 16-bit timer 0 x x x 00 16-bit event counter 1 x x x 01 or 10 or 11 16-bit capture (internal clock) 1 x x x 00 16-bit capture (external clock) table 11-2 tm2 timer mode register
gms81508b/16b/24b, gms82512/16/24 40 may. 2001 ver 2.0 figure 11-1 tm0, tm2 registers btcl 76543210 t3st cap2 t2sl1 initial value: 00 h address: 0e3 h tm2 t2sl0 t2cn t2st t3sl1 t3sl0 bit name bit posi- tion description cap2 tm2.7 0: timer/counter mode 1: capture mode selection flag t3st tm2.6 0: when cleared, stop the counting. 1: when set, timer 3 count register is cleared and start again. t3sl1 t3sl0 tm2.5 tm2.4 00: 16-bit mode (clock source is selected by t2sl1, t2sl0) 01: 8-bit mode, clock source is f xin ? 4 10: 8-bit mode, clock source is f xin ? 16 11: 8-bit mode, clock source is f xin ? 64 t2st tm2.3 0: when cleared, stop the counting. 1: when set, timer 2 count register is cleared and start again. t2cn tm2.2 0: stop the timer 1: a logic 1 starts the timer. t2sl1 t2sl0 tm2.1 tm2.0 00: ec2 (external clock) 01: 8-bit timer, clock source is f xin ? 4 10: 8-bit timer, clock source is f xin ? 16 11: 8-bit timer, clock source is f xin ? 64 timer 2 btcl 76543210 t1st cap0 t0sl1 initial value: 00 h address: 0e2 h tm0 t0sl0 t0cn t0st t1sl1 t1sl0 bit name bit position description cap0 tm0.7 0: timer/counter mode 1: capture mode selection flag t1st tm0.6 0: when cleared, stop the counting. 1: when set, timer 1 count register is cleared and start again. t1sl1 t1sl0 tm0.5 tm0.4 00: 16-bit mode (clock source is selected by t0sl1, t0sl0) 01: 8-bit mode, clock source is f xin ? 4 10: 8-bit mode, clock source is f xin ? 16 11: 8-bit mode, clock source is f xin ? 64 t0st tm0.3 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. t0cn tm0.2 0: stop the timer 1: a logic 1 starts the timer. t0sl1 t0sl0 tm0.1 tm0.0 00: ec0 (external clock) 01: 8-bit timer, clock source is f xin ? 4 10: 8-bit timer, clock source is f xin ? 16 11: 8-bit timer, clock source is f xin ? 64 timer 1 timer 0 76543210 initial value: undefined address: 0e4 h ~ 0e7 h tdr0~tdr3 read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w timer 3
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 41 11.1 8-bit timer / counter mode the gms815xxb and gms825xx have four 8-bit timer/ counters, timer 0, timer 1, timer 2, timer 3. the timer 0, timer 1 are shown in figure . the timer or counter function is selected by control registers tm0, tm2 as shown in table 11-1 and table 11- 2. to use as an 8-bit timer/counter mode, bit cap0 of tm0 is cleared to 0 and bits t1sl1, t1sl0 of tm0 or bits t3sl1, t3sl0 of tm2 should not set to zero. these timers have each 8-bit count register and data register. the count register is increased by every internal or external clock in- put. the internal clock has a prescaler divide ratio option of 4, 16, 64 (selected by control bits txsl1, txsl0 of reg- ister tmx). figure 11-2 8-bit timer/counter 0, 1 example 1: timer0 = 4ms 8-bit timer mode at 4mhz timer1 = 1ms 8-bit timer mode at 4mhz ldm tdr0,#250 ldm tdr1,#250 ldm tm0,#0110_1111b set1 t0e set1 t1e ei example 2: timer0 = 8-bit event counter mode timer1 = 1ms 8-bit timer mode at 4mhz ldm tdr0,#250 ldm tdr1,#250 ldm tm0,#0110_1100b set1 t0e set1 t1e ei ec0 pin ? 4 ? 16 ? 64 xin pin mux prescaler t0if clear 0: stop 1: clear and start t0st t0sl[1:0] 00 01 10 11 timer 0 interrupt t0cn mux t1if clear 0: stop 1: clear and start t1st t1sl[1:0] 01 10 11 timer 1 interrupt ? 4 ? 16 ? 64 tdr0 (8-bit) tdr1 (8-bit) t1 (8-bit) t0 (8-bit) comparator comparator timer 0 timer 1 t1o pin f/f btcl 76543210 t1st cap0 t0sl1 initial value: 00 h address: 0e2 h tm0 t0sl0 t0cn t0st t1sl1 t1sl0 0x xx x x x means dont care 01 or 10 or 11
gms81508b/16b/24b, gms82512/16/24 42 may. 2001 ver 2.0 note: the contents of timer data register tdrx should be initialized 1 h ~ff h , not 0 h , because it is undefined after re- set. in the timer 0, timer register t0 increments from 00 h until it matches tdr0 and then reset to 00h. the match output of timer 0 generates timer 0 interrupt (latched in t0if bit) as tdrx and tx register are in same address, when read- ing it as a tx, written to tdrx. in counter function, the counter is increased every 1-to-0 (falling edge) transition of ec0 or ec2 pin. in order to use counter function, the bit 4, bit 5 of the port mode register pmr4 are set to 1. the timer 0 can be used as a counter by pin ec0 input, but timer 1 can input by internal clock. similarly, timer 2 can be used by pin ec2 input but timer 3 can not. ec2 are not served on gms825xx. figure 11-3 8-bit timer/counter 2, 3 example 3: timer2 = 8-bit timer mode, 2ms interval at 8mhz timer3 = 8-bit timer mode, 500us interval at 8mhz ldm tdr2,#250 ldm tdr3,#250 ldm tm2,#0110_1111b set1 t2e set1 t3e ei example 4: timer2 = 8-bit event counter mode timer3 = 500us 8-bit timer mode at 8mhz ldm tdr2,#250 ldm tdr3,#250 ldm tm2,#0110_1100b set1 t2e set1 t3e ei ec2 pin ? 4 ? 16 ? 64 xin pin mux prescaler t2if clear 0: stop 1: clear and start t2st t2sl[1:0] 00 01 10 11 timer 2 interrupt t2cn mux t3if clear 0: stop 1: clear and start t3st t3sl[1:0] 01 10 11 timer 3 interrupt ? 4 ? 16 ? 64 tdr2 (8-bit) tdr3 (8-bit) t3 (8-bit) t2 (8-bit) comparator comparator timer 2 timer 3 t3o pin f/f btcl 76543210 t3st cap2 t2sl1 initial value: 00 h address: 0e3 h tm2 t2sl0 t2cn t2st t3sl1 t3sl0 0x xx x x x means dont care 01 or 10 or 11 edge detector
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 43 8-bit timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock in- put. the contents of tdr n are compared with the contents of up-counter, t n . if match is found, a timer 1 interrupt (t1if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr n is changeable by software, time in- terval is set as you want figure 11-4 timer mode timing chart figure 11-5 timer count example value of tm[1:0] clock source resolution (at f xin =8 mhz) maximum time setting (at f xin =8 mhz) 00 01 10 11 f ec1 f xin ? 4 f xin ? 16 f xin ? 64 1/f ec1 0.5 2 8 sec us us us 1/f ec1 256 128 512 2048 sec us us us table 11-1 timer source clock interrupt time 0 n-2 2 0 n 3 n-1 n source clock up-counter tdr1 t1if interrupt start count 1 23 1 4 match detect counter clear ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period u p -c oun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7a 7d 7c count pulse = 8 m s x 125 7b match example: make 1ms interrupt using by timer0 at 8mhz ldm tm0,#1fh ; divide by 64 ldm tdr0,#125 ; 8us x 125= 1ms set1 t0e ; enable timer 0 interrupt ei ; enable master interrupt period when tdr0 = 125 d = 7d h f xin = 8 mhz interrupt period = 8 106 hz 1 64 125 = 1 ms tm0 = 0001 1111 b (8-bit timer mode, prescaler divide ratio = 64) 8 m s (tdr0 = t0) 7d 0
gms81508b/16b/24b, gms82512/16/24 44 may. 2001 ver 2.0 8-bit event counter mode in this mode, counting up is started by an external trigger. this trigger means falling edge of the ec0 or ec2 pin in- put. source clock is used as an internal clock selected with timer mode register tm0 or tm2. the contents of timer data register tdr n (n = 0,1,2,3) are compared with the contents of the up-counter t n . if a match is found, an timer interrupt request flag t n if is generated, and the counter is cleared to 0. the counter is restart and count up contin- uously by every falling edge of the ec n pin input. the maximum frequency applied to the ec n pin is f xin /2 [hz]. in order to use event counter function, the bit 4, 5 of the port mode register pmr4(address 0d0 h ) is required to be set to 1. ec2 are not served on gms825xx. after reset, the value of timer data register tdr n is unde- fined, it should be initialized to between 1 h ~ff h not to "0"the interval period of timer is calculated as below equation. figure 11-6 event counter mode timing chart figure 11-7 count operation of timer / event counter period (sec) 1 f xin ---------- - 2 divide ratio tdrn = 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ec n pin input up-counter tdr1 t1if interrupt start count timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up -c ou n t ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 45 11.2 16-bit timer / counter mode the timer register is being run with all 16 bits. a 16-bit timer/counter register t0, t1 are incremented from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 interrupt. the clock source of the timer 0 is selected either internal or external clock by bit t0sl1, t0sl0. even if the timer 0 (including the timer 1) is used as a 16- bit timer, the timer 2 and timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the tm2. re- versely, even if the timer 2 (including the timer 3) is used as a 16-bit timer, the timer 0 and timer 1 can still be used as 8-bit timer independently. figure 11-8 16-bit timer/counter ec0 pin ? 4 ? 16 ? 64 xin pin mux prescaler t0if clear 0: stop 1: clear and start t0st t0sl[1:0] 00 01 10 11 timer 0 interrupt t0cn tdr1 + tdr0 comparator timer 0 + timer 1 ? timer 0 (16-bit) higher byte lower byte (16-bit) compare data t1 + t0 (16-bit) 1 0 (not timer 1 interrupt) edge detector btcl 76543210 t1st cap0 t0sl1 initial value: 00 h address: 0e2 h tm0 t0sl0 t0cn t0st t1sl1 t1sl0 0x xx x x 00 x means dont care ec2 pin ? 4 ? 16 ? 64 xin pin mux prescaler t2if clear 0: stop 1: clear and start t2st t2sl[1:0] 00 01 10 11 timer 2 interrupt t2cn tdr3 + tdr2 comparator timer 2 + timer 3 ? timer 2 (16-bit) higher byte lower byte (16-bit) compare data t3 + t2 (16-bit) 1 0 (not timer 3 interrupt) edge detector btcl 76543210 t3st cap2 t2sl1 initial value: 00 h address: 0e3 h tm2 t2sl0 t2cn t2st t3sl1 t3sl0 0x xx x x 00 x means dont care
gms81508b/16b/24b, gms82512/16/24 46 may. 2001 ver 2.0 11.3 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap2 of timer mode register tm2 for timer 2) as shown in figure 21. in this mode, timer 1 still operates as an 8-bit timer/counter. as mentioned above, not only timer 0 but timer 2 can also be used as a capture mode. in 8-bit capture mode, timer 1 and timer 3 are can not be used as a capture mode. the timer/counter register is incremented in response in- ternal or external input. this counting function is same with normal timer mode, but timer interrupt is not gener- ated. timer/counter still does the above, but with the add- ed feature that a edge transition at external input int n pin causes the current value in the timer counter register (t0,t2), to be captured into registers cdr n (cdr0, cdr2), respectively. after captured, timer counter regis- ter is cleared and restarts by hardware. note: the cdrn and tdrn are in same address.in the capture mode, reading operation is read the cdrn, not tdrn because path is opened to the cdrn. it has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register ieds. refer to 16.4 external interrupt on page 64. in addition, the transition at int n pin generate an inter- rupt. figure 11-9 8-bit capture mode ec0 pin ? 4 ? 16 ? 64 xin pin mux prescaler int0if 0: stop 1: clear and start t0st t0sl[1:0] 00 01 10 11 int0 interrupt t0cn cdr0 (8-bit) t0 (8-bit) timer 0 btcl 76543210 t1st cap0 t0sl1 initial value: 00 h address: 0e2 h tm0 t0sl0 t0cn t0st t1sl1 t1sl0 1x xx x x x means dont care 01 or 10 or 11 01 10 11 int0 pin capture to timer1 ieds[1:0] edge detector this figure is a example of using the timer0. in the timer2, operation is same like timer0, each registers and flags may be changed with for timer2.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 47 11.4 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. figure 11-10 16-bit capture mode ec0 pin ? 4 ? 16 ? 64 xin pin mux prescaler int0if 0: stop 1: clear and start t0st t0sl[1:0] 00 01 10 11 int0 interrupt t0cn btcl 76543210 t1st cap0 t0sl1 initial value: 00 h address: 0e2 h tm0 t0sl0 t0cn t0st t1sl1 t1sl0 1x xx x x x means dont care 01 10 11 int0 pin capture ieds[1:0] edge detector this figure is a example of using the timer0, 1. in the timer2, 3, operation is same like timer0,1, each registers and flags may be changed with for timer2,3. cdr1 + cdr0 higher byte lower byte (16-bit) capture data t1 + t0 (16-bit) 0 0 timer 0 + timer 1 ? timer 0 (16-bit)
gms81508b/16b/24b, gms82512/16/24 48 may. 2001 ver 2.0 example 1: timer0 = 16-bit timer mode, 0.5s at 8mhz timer2 = 2ms 8-bit timer mode at 8mhz timer3 = 250us 8-bit timer mode at 8mhz ldm tdr0,#23h ldm tdr1,#0f4h ldm tm0,#0fh ldm tdr2,#249 ldm tdr3,#124 ldm tm2,#0110_1111b set1 t0e set1 t2e set1 t3e ei : : example 2: timer0 = 8-bit timer mode, 2ms interval at 8mhz timer2 = 16-bit event counter mode ldm tdr0,#249 ldm tm0,#0111_1111b ldm tdr2,#3fh ldm tdr3,#2ah ldm tm2,#0100_1100b set1 t0e set1 t2e ei : : example 3: timer0 = 8-bit timer mode, 2ms interval at 8mhz timer2 = 8-bit capture mode ldm tdr0,#250 ldm tm0,#0111_1111b set1 t0e ldm tdr2,#40h ldm tdr3,#2ah ldm tm2,#1111_1111b set1 t2e ldm ieds,#xx11_xxxxb ldm pmr4,#xxxx_x1xxb set1 int2e ei : : x: dont care. example 4: timer0 = 8-bit timer mode, 2ms interval at 8mhz timer2 = 16-bit capture mode ldm tdr0,#249 ldm tm0,#0111_1111b set1 t0e ldm tdr2,#40h ldm tdr3,#2ah ldm tm2,#1100_1111b set1 t2e ldm ieds,#xx11_xxxxb ldm pmr4,#xxxx_x1xxb set1 int2e ei : : x: dont care.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 49 12. analog digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog supply voltage is connected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the control register adcm and a/d result register adr. the register adcm, shown in figure 12-2, controls the operation of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, i/o is selected input mode by r6dd direction register. r60 ~ r63 are not served on gms825xx. how to use a/d converter the processing of conversion is start when the start bit adst is set to 1. after one cycle, it is cleared by hard- ware. the register adr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adr, the a/d conversion status bit adsf is set to 1, and the a/d interrupt flag aif is set. the block diagram of the a/d module is shown in figure 12-1. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conver- sion is in process. the conversion time takes maximum 20 us (at f xin =8 mhz). figure 12-1 a/d block diagram note: on the mds(choice-dr,jr), when the mcu is re- set, r60 port is selected as an analog input by adcm reg- ister. so it can not be used digital input port. to use this port as a digital i/o port, change to except 0 the value of ad- cm. finally all eight ports can not be used as digital i/o port simultaneously on the mds. at least one port must be in an- alog port. but on the otp and main chip, r6 port, all eight pins can be used as digital i/o port at the same time. * r60/an0 * r61/an1 * r62/an2 * r63/an3 r64/an4 r65/an5 r66/an6 r67/an7 s/h sample & hold 0 1 aden av dd 8-bit dac ladder resistor adif a/d interrupt successive approximation circuit adr a/d result register address: e9 h reset value: undefined 000 001 010 011 100 101 110 111 ads[2:0] * these ports are not served on the gms825xx.
gms81508b/16b/24b, gms82512/16/24 50 may. 2001 ver 2.0 figure 12-2 a/d converter control register btcl 76543210 - - adst a/d status bit analog input channel select initial value: --00 0001 b address: 0e8 h adcm adsf a/d converter enable bit 0: a/d converter module turn off and current is not flow. 1: enable a/d converter r/w r/w r/w r/w r/w r * 000: channel 0 (an0) * 001: channel 1 (an1) * 010: channel 2 (an2) * 011: channel 3 (an3) 100: channel 4 (an4) 101: channel 5 (an5) 110: channel 6 (an6) 111: channel 7 (an7) 0: a/d conversion is in progress 1: a/d conversion is completed a/d start bit setting this bit starts an a/d conversion. after one cycle, bit is cleared to 0 by hardware. ads1 ads0 aden ads2 initial value: undefined address: 0e9 h adr a/d conversion data btcl 76543210 rrrr rr r r * these are not served on the gms825xx.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 51 13. serial communication - this function is not served on the gms825xx. the serial iterface is used to transmit/receive 8-bit data se- rially. this consists of serial i/o data register, serial i/o mode register, clock selection circuit octal counter and control circuit as illustrated in figure 13-1.pin r50/sin, r51/sout, r52/sclk and r53/srdy pins are con- trolled by the serial mode register. the contents of the se- rial i/o data register can be written into or read out by software. the data in the serial data register can be shift- ed synchronously with the transfer clock signal. figure 13-1 sci block diagram srdy pin ? 8 ? 16 ? 32 xin pin prescaler mux sck[1:0] 00 01 10 11 sclk pin start control circuit sin pin shift input shift register sior clock clock octal serial communication interrupt sioif sout pin siost siosf complete r s q counter sck[1:0] 11 overflow not 11 srdy in complete srdy out [0eb h ] internal bus line
gms81508b/16b/24b, gms82512/16/24 52 may. 2001 ver 2.0 serial i/o mode register(siom) controls serial i/o func- tion. according to sck1 and sck0, the internal clock or external clock can be selected. serial i/o data register(sior) is an 8-bit shift register. first lsb is send or is received. figure 13-2 sci control register btcl 76543210 srdy - siost serial transmission status bit serial transmission clock selection initial value: -000 0001 b address: 0ea h siom siosf r53/srdy selection 0: r53 1: srdy r/w r/w r/w r/w r/w r 00: f xin ? 4 01: f xin ? 16 10: f xin ? 32 11: external clock 0: serial transmission is in progress 1: serial transmission is completed serial transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to 0 by hardware. sck1 sck0 sm1 sm0 r/w serial transmission operation mode 00: normal port(r52,r51,r50) 01: sending mode(sclk,sout,r50) 10: receiving mode(sclk,r51,sin) 11: sending & receiving mode(sclk,sout,sin) initial value: undefined address: 0eb h sior btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data at sending mode receiving data at receiving mode
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 53 13.1 transmission/receiving timing the serial transmission is started by setting siost(bit1 of siom) to 1. after one cycle of sck, siost is cleared automatically to 0. the serial output data from 8-bit shift register is output at falling edge of sclk. and input data is latched at rising edge of sclk pin. when transmission clock is counted 8 times, serial i/o counter is cleared as 0. transmission clock is halted in h state and serial i/ o interrupt(ifsio) occurred. figure 13-3 timing diagram of serial i/o 13.2 the serial i/o operation by srdy pin transmission clock = external clock the srdy pin becomes l by siost = 1. this signal tells to the external system that this device is ready for se- rial transmission. the external system detects the l sig- nal and starts transmission. the srdy pin becomes h at the first rising edge of transmission clock. transmission clock = internal clock the i/o of srdy pin is input mode. when the external system is ready for serial transmission, the l level is in- putted at this pin. at this time this device starts serial trans- mission. d1 d0 siost flag sout pin input clock sclk pin d4 d3 d2 d7 d6 d5 d1 d0 sin pin d4 d3 d2 d7 d6 d5 sioif output latch interrupt signal srdy (output) siost srdy (input) siost
gms81508b/16b/24b, gms82512/16/24 54 may. 2001 ver 2.0 13.3 the method of serial i/o 1. select transmission/receiving mode. 2. in case of sending mode, write data to be send to sior. 3. set siost to 1 to start serial transmission. 4. the sio interrupt is generated at the completion of sio and siosf is set to 1. in sio interrupt service routine, correct transmission should be tested. 5. in case of receiving mode, the received data is acquired by reading the sior. note: when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. if both transmission mode is selected and transmission is per- formed simultaneously it would be made error. 13.4 the method to test correct transmission figure 13-4 serial method to test transmission serial i/o interrupt service routine se = 0 write siom normal operation overrun error abnormal siosf 0 1 - se: interrupt enable register low ienl(bit3) - sr: interrupt request flag register low irql(bit3) sr 0 1
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 55 14. pwm output - this function is not served on the gms825xx. the gms815xxb have two channels of built-in pulse width modulation outputs. pwm outputs data are multi- plex to the r56 and r57 port. bit 6 and bit 7 of r5dd should be set to 1 when pwm is used as an output port. the input clock is selected by pwm control register (pwmcr, address f2 h ) and the width of pulse is deter- mined by the pwm register (pwmr, address f0 h and f1 h ). figure 14-1 pwm block diagram the pulse period according to input clock are shown as be- low. bit 2 (en0) and bit 3 (en1) of pwmcr determine the op- eration channel of pwm. when en0=0 and en1=0, pwm does not execute it is a pwm output controlled by pwmcr, pwmr0 and pwmr1. f xin ? 256 mux s p0ck[1:0] 00 01 10 11 pwm0 comparator 8-bit counter f xin ? 512 f xin ? 1024 f xin ? 2048 r pwmr0 q overflow f xin ? 2048 mux s p1ck[1:0] 11 10 01 00 comparator 8-bit counter f xin ? 1024 f xin ? 512 f xin ? 256 r pwmr1 q overflow pol0 pwm1 pol1 en0 en1 0 1 0 1 f/f f/f [0f0 h ] [0f1 h ] input clock period of pwm f xin ? ? ? ? 256 f xin ? ? ? ? 512 f xin ? ? ? ? 1024 f xin ? ? ? ? 2048 8.19 ms 16.38 ms 32.77 ms 65.54 ms duty ratio pwmr 1 + 256 --------------------------- - 100% =
gms81508b/16b/24b, gms82512/16/24 56 may. 2001 ver 2.0 figure 14-2 pwm duty register figure 14-3 pwm control register example: pwm0: period = 16.384ms, duty = 20% pwm1: period = 8.192ms, duty = 70% ldm pwmcr,#0100_1111b ldm pwmr0,#0b3h ldm pwmr1,#33h pwmr0 address: 0f0 h reset value: undefined duty data pwmr1 address: 0f1 h reset value: undefined duty data wwww wwww wwww wwww btcl 76543210 p1ck0 p1ck1 pol1 pwm0 output polarity pwm enable flag initial value: 0000 0000 b address: 0f2 h pwmcr pol0 pwm0 clock selection 00: f xin ? 256 wwwwww 00: disable(r56,r57) 01: pwm0(pwm0,r57) 10: pwm1(r56,pwm1) 11: both (pwm0, pwm1) 0: active low 1: active high en1 en0 p0ck1 p0ck0 ww pwm1 output polarity 0: active low 1: active high 01: f xin ? 512 10: f xin ? 1024 11: f xin ? 2048 pwm1 clock selection 00: f xin ? 256 01: f xin ? 512 10: f xin ? 1024 11: f xin ? 2048
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 57 figure 14-4 example of register setting 3.264ms 16.384ms pwm1 8mhz 512 256 ? ? 61.035hz = 01 8mhz 256 256 ? ? 122.07hz = 8.192ms 00 111 1 enable active high pwm0 16.384 33 h 100 h ------------ - 3.264ms = 8.192 b3 h 100 h ------------ - 5.728ms = 5.728ms pwmcr pwmr1 pwmr0 f xin fixed f xin fixed
gms81508b/16b/24b, gms82512/16/24 58 may. 2001 ver 2.0 15. buzzer function the buzzer driver block consists of 6-bit binary counter, buzzer register, and clock source selector. it generates square-wave which has very wide range frequency (500hz ~ 250khz at f xin = 8mhz) by user software. a 50% duty pulse can be output to r55/buz pin to use for piezo-electric buzzer drive . pin r55 is assigned for output port of buzzer driver by setting the bit 5 of pmr5 (address d1 h ) to 1. at this time, the pin r55 must be defined as output mode (the bit 5 of r5dd=1). example: 2.4khz output at 8mhz. ldm r5dd,#xx1x_xxxxb ldm bur,#9ah ldm pmr5,#xx1x_xxxxb x means dont care the bit 0 to 5 of bur determines output frequency for buzzer driving. equation of frequency calculation is shown below. f buz : buzzer frequency f xin : oscillator frequency divide ratio: prescaler divide ratio by buck[1:0] bur: lower 6-bit value of bur. buzzer period value. the frequency of output signal is controlled by the buzzer control register bur.the bit 0 to bit 5 of bur determine output frequency for buzzer driving. figure 15-1 block diagram of buzzer driver figure 15-2 pmr5 and buzzer register f buz f xin 2 divideratio bur ------------------------------------------------------------- = prescaler ? 16 ? 64 ? 32 ? 128 bur r55/buz pin pmr5 internal bus line r55 port data xin pin 6-bit binary 2 6 [0ec h ] [0d1 h ] 0 1 f/f ? 2 comparator compare data 6-bit counter mux 00 01 10 11 port selection bur[5:0] bur address: 0ec h reset value: undefined w wwww w source clock select 00: ? 16 01: ? 32 10: ? 64 11: ? 128 buzzer period data r55/buz selection pmr5 address: 0d1 h reset value: --00 ---- b w - - 0: r55 port (turn off buzzer) 1: buz port (turn on buzzer) ww -- - - w r54/wdto selection 0: r54 1: wdto (output) buck1 buck0
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 59 note: bur is undefined after reset, so it must be initialized to between 1 h and 3f h by software. note that bur is a write-only register. the 6-bit counter is cleared and starts the counting by writ- ing signal at bur register. it is incremental from 00 h until it matches 6-bit bur value. when main-frequency is 8mhz, buzzer frequency is shown as below table. [khz] bur [5:0] bur[7:6] bur [5:0] bur[7:6] 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 - 250.000 125.000 83.333 62.500 50.000 41.667 35.714 - 125.000 62.500 41.667 31.250 25.000 20.833 17.857 - 62.500 31.250 20.833 15.625 12.500 10.417 8.929 - 31.250 15.625 10.417 7.813 6.250 5.208 4.464 20 21 22 23 24 25 26 27 7.813 7.576 7.353 7.143 6.944 6.757 6.579 6.410 3.906 3.788 3.676 3.571 3.472 3.378 3.289 3.205 1.953 1.894 1.838 1.786 1.736 1.689 1.645 1.603 0.977 0.947 0.919 0.893 0.868 0.845 0.822 0.801 08 09 0a 0b 0c 0d 0e 0f 31.250 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 28 29 2a 2b 2c 2d 2e 2f 6.250 6.098 5.952 5.814 5.682 5.556 5.435 5.319 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 1.563 1.524 1.488 1.453 1.420 1.389 1.359 1.330 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 10 11 12 13 14 15 16 17 15.625 14.706 13.889 13.158 12.500 11.905 11.364 10.870 7.813 7.353 6.944 6.579 6.250 5.952 5.682 5.435 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.717 1.953 1.838 1.736 1.645 1.563 1.488 1.420 1.359 30 31 32 33 34 35 36 37 5.208 5.102 5.000 4.902 4.808 4.717 4.630 4.545 2.604 2.551 2.500 2.451 2.404 2.358 2.315 2.273 1.302 1.276 1.250 1.225 1.202 1.179 1.157 1.136 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 18 19 1a 1b 1c 1d 1e 1f 10.417 10.000 9.615 9.259 8.929 8.621 8.333 8.065 5.208 5.000 4.808 4.630 4.464 4.310 4.167 4.032 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.302 1.250 1.202 1.157 1.116 1.078 1.042 1.008 38 39 3a 3b 3c 3d 3e 3f 4.464 4.386 4.310 4.237 4.167 4.098 4.032 3.968 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 table 15-1 buzzer frequency
gms81508b/16b/24b, gms82512/16/24 60 may. 2001 ver 2.0 16. interrupts the gms815xxb and gms825xx interrupt circuits con- sist of interrupt enable register (ienh, ienl), interrupt re- quest flags of irqh, irql, priority circuit, and master enable flag (i flag of psw). thirteen interrupt(twelve interrupt in case of gms825xx) sources are provided. the configuration of interrupt circuit is shown in figure 16-2. the external interrupts int0 ~ int3 each can be transi- tion-activated (1-to-0 or 0-to-1 transition) by selection ieds. the flags that actually generate these interrupts are bit int0f, int1f, int2f and int3f in register irqh. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vec- tored to only if the interrupt was transition-activated. the timer 0 ~ timer 3 interrupts are generated by txif which is set by a match in their respective timer/counter register. the basic interval timer interrupt is generated by bitif which is set by an overflow in the timer register. the ad converter interrupt is generated by adif which is set by finishing the analog to digital conversion. the watchdog timer interrupt is generated by wdtif which set by a match in watchdog timer register. the basic interval timer interrupt is generated by bitif which are set by a overflow in the timer counter register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw on page 22), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk interrupt. below table shows the interrupt priority. * this interrupt is not served on gms825xx. vector addresses are shown in figure 8-6 on page 24. in- terrupt enable registers are shown in figure 16-3. these registers are composed of interrupt enable flags of each in- terrupt source and these flags determines whether an inter- rupt will be accepted or not. when enable flag is 0, a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which dis- ables all interrupts at once. figure 16-1 interrupt request flag reset/interrupt symbol priority hardware reset external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 timer/counter 0 timer/counter 1 timer/counter 2 timer/counter 3 adc interrupt basic interval timer watchdog timer * serial communication reset int0 int1 int2 int3 timer 0 timer 1 timer 2 timer 3 adc bit wdt sci 1 2 3 4 5 6 7 8 9 10 11 12 13 int3if r/w int0if timer/counter 3 interrupt request flag initial value: 0000 0000 b address: 0f7 h irqh int1if msb lsb t2if t3if t0if t1if int2if r/w r/w timer/counter 2 interrupt request flag timer/counter 1 interrupt request flag external interrupt 3 request flag * sioif r/w adif serial communication interrupt request flag initial value: 0000 ---- b address: 0f5 h irql wdtif msb lsb - - - bitif r/w timer/counter 0 interrupt request flag r/w r/w - r/w r/w r/w r/w r/w - - -- basic interval timer interrupt request flag watchdog timer interrupt request flag a/d converter interrupt request flag external interrupt 3 request flag external interrupt 3 request flag external interrupt 3 request flag * this is not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 61 . figure 16-2 block diagram of interrupt figure 16-3 interrupt enable flag timer 0 int2 int1 int0 int0if ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i-flag ienl priority control i-flag is in psw, it is cleared by di, set by ei instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. [0f6 h ] [0f4 h ] [0f7 h ] [0f5 h ] int1if int2if int3if t0if t3if t2if int3 timer 1 timer 3 timer 2 t1if a/d converter adif * sioif bitif watchdog timer * serial bit wdtif communication * this is not served on gms825xx. int3e r/w int0e timer/counter 3 interrupt enable flag initial value: 0000 0000 b address: 0f6 h ienh int1e msb lsb t2e t3e t0e t1e int2e r/w r/w timer/counter 2 interrupt enable flag timer/counter 1 interrupt enable flag external interrupt 3 enable flag * sioe r/w ade serial communication interrupt enable flag initial value: 0000 ---- b address: 0f4 h ienl wdte msb lsb - - - bite r/w timer/counter 0 interrupt enable flag r/w r/w - r/w r/w r/w r/w r/w - - -- basic interval timer interrupt enable flag watchdog timer interrupt enable flag a/d converter interrupt enable flag external interrupt 2 enable flag external interrupt 1 enable flag external interrupt 0 enable flag 0: disable 1: enable value * this is not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 62 may. 2001 ver 2.0 16.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an in- struction. interrupt acceptance sequence requires 8 f xin (2 m s at f main =4.19mhz) after the completion of the current instruction execution. the interrupt service task is termi- nated upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. figure 16-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 63 area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; 16.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 16-5. figure 16-5 execution of brk/tcall0 intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
gms81508b/16b/24b, gms82512/16/24 64 may. 2001 ver 2.0 16.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. figure 16-6 execution of multi interrupt however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. example: during timer1 interrupt is in progress, int0 in- terrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0f0h pop y pop x pop a reti 16.4 external interrupt the external interrupt on int0, int1, int2 and int3 pins are edge triggered depending on the edge selection register ieds (address 0f8 h ) as shown in figure 16-7. the edge detection of external interrupt has three transition enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable ei in the timer1 routine.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 65 activated mode: rising edge, falling edge, and both edge. figure 16-7 external interrupt block diagram int0 ~ int3 are multiplexed with general i/o ports (r40~r43). to use as an external interrupt pin, the bit of r4 port mode register pmr4 should be set to 1 corre- spondingly. example: to use as an int0 and int2 : : ; **** set port as an input port r40,r42 ldm r4dd,#1111_1010b ; ; **** set port as an external interrupt port ldm pmr4,#05h ; ; **** set falling-edge detection ldm ieds,#0001_0001b : : : response time the int0 ~ int3 edge are latched into int1if ~ int3if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 16-8shows interrupt response timings. figure 16-8 interrupt response timing diagram int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt ieds [0f8h] int3if int3 pin int3 interrupt edge selection register 2 2 2 2 interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin max. 12 f xin
gms81508b/16b/24b, gms82512/16/24 66 may. 2001 ver 2.0 figure 16-9 pmr4 and ieds registers btcl wwwwwwww * ec2s * t1s * t3s int1s 0: r40 1: int0 initial value: 00 h address: 0d0 h pmr4 ec0s int0s int2s int3s 0: r41 1: int1 0: r42 1: int2 0: r43 1: int3 0: r47 1: t3o 0: r46 1: t1o 0: r45 1: ec2 0: r44 1: ec0 lsb msb btcl wwwwwwww ied2h ied3l ied3h ied0h initial value: 00 h address: 0f8 h ieds ied2l ied0l ied1l ied1h lsb msb edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int0 int1 int2 int3 * these are not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 67 17. watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and re- sumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. figure 17-1 block diagram of watchdog timer watchdog timer control figure 17-2 shows the watchdog timer control register. the watchdog timer is automatically disabled after reset. the cpu malfunction is detected during setting of the de- tection time, selecting of output, and clearing of the binary counter. clearing the binary counter is repeated within the detection time. if the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. at this time, when wdton=1, a reset is generated, which drives the reset pin to low to reset the internal hardware. when wdton=0, a watchdog timer interrupt (wdtif) is generated. the watchdog timer temporarily stops counting in the stop mode, and when the stop mode is released, it au- tomatically restarts (continues counting). figure 17-2 wdtr: watchdog timer data register to reset cpu basic interval timer count source enable watchdog 6-bit compare data comparator watchdog timer interrupt clear clear wdtif counter (8-bit) wdtcl 0 1 wdton in ckctlr [0d3 h ] overflow watchdog timer register wdtr internal bus line 6 [0e0 h ] 76543210 wdtcl - clear count flag 0: free-run count initial value: -011_1111 b address: 0e0 h wdtr ww ww 1: when the wdtcl is set to 1, binary counter is cleared to 0. and the wdtcl becomes 0 automatically after one machine cycle. counter count up again. 6-bit compare data wwww note: the wdton bit is in register ckctlr.
gms81508b/16b/24b, gms82512/16/24 68 may. 2001 ver 2.0 example: sets the watchdog timer detection time to 0.5 sec at 4.19mhz enable and disable watchdog watchdog timer is enabled by setting wdton (bit 5 in ckctlr) to 1. wdton is initialized to 0 during re- set and it should be set to 1 to operate after reset is re- leased. example: enables watchdog timer for reset : ldm ckctlr,#xx1x_xxxxb; wdton ? 1 : : the watchdog timer is disabled by clearing bit 5 (wd- ton) of ckctlr. the watchdog timer is halted in stop mode and restarts automatically after stop mode is re- leased. watchdog timer interrupt the watchdog timer can be also used as a simple 6-bit tim- er by clearing bit5 of ckctlr to 0. the interval of watchdog timer interrupt is decided by basic interval tim- er. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 6-bit timer interrupt set up. ldm ckctlr,#xx0xxxxxb; wdton ? 0 ldm wdtr,#7fh ; wdtcl ? 1 : figure 17-3 watchdog timer timing if the watchdog timer output becomes active, a reset is gen- erated, which drives the reset pin low to reset the inter- nal hardware. the main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. ldm ckctlr,#3fh ; select 1/2048 clock source , wdton ? 1, clear counter ldm wdtr,#04fh ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter within wdt detection time within wdt detection time t wdtr interval of bit = 2 3 n source clock binary-counter wdtr wdtif interrupt wdtr ? 0100_0011 b 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 69 18. power down operation gms815xxb has a power-down mode. in power-down mode, power consumption is reduced considerably that in battery operation. battery life can be extended a lot. stop mode is entered by stop instruction. 18.1 stop mode for applications where power consumption is a critical factor, device provides reduced power of stop. start the stop operation an instruction that stop causes to be the last instruction is executed before going into the stop mode. in the stop mode, the on-chip main-frequency oscillator is stopped. with the clock frozen, all functions are stopped, but the on- chip ram and control registers are held. the port pins output the values held by their respective port data register, the port direction registers. the status of peripherals during stop mode is shown below. note: since the x in pin is connected internally to gnd to avoid current leakage due to the crystal oscillator in stop mode, do not use stop instruction when an external clock is used as the main system clock. in the stop mode of operation, v dd can be reduced to min- imize power consumption. be careful, however, that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. and after stop instruction, at least two or more nop in- struction should be written as shown in example below. example: ldm ckctlr,#0000_1110b stop nop nop : the interval timer register ckctlr should be initial- ized (0f h or 0e h ) by software in order that oscillation sta- bilization time should be longer than 20ms before stop mode. figure 18-1 stop mode release timing by external interrupt peripheral stop mode cpu all cpu operations are disabled ram retain x in pin low x out pin high oscillation stop i/o ports retain control registers retain release method by reset, by external interrupt before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~
gms81508b/16b/24b, gms82512/16/24 70 may. 2001 ver 2.0 release the stop mode the exit from stop mode is using hardware reset or exter- nal interrupt. to release stop mode, corresponding interrupt should be enabled before stop mode. reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. start-up is performed to acquire the time for stabilizing os- cillation. during the start-up, the internal operations are all stopped. 18.2 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly in order that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there event mcu status before event chip function after event pc oscillator circuit reset dont care vector on stop instruction normal operation n +1 off external interrupt normal operation vector on external interrupt wake up stop, i flag = 1 stop, i flag = 0 vector n + 1 on on table 18-1 wake-up and reset function table
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 71 is external pull-down register, it is set to low. figure 18-2 application example of unused input port figure 18-3 application example of unused output port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configure as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port.
gms81508b/16b/24b, gms82512/16/24 72 may. 2001 ver 2.0 19. oscillator circuit the gms815xxb has two oscillation circuits internally. x in and x out are input and output for frequency, respec- tively, inverting amplifier which can be configured for be- ing used as an on-chip oscillator, as shown in figure 19-1. figure 19-1 oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. in addition, see figure 19-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 19-2 layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 30pf10pf c1 c2 x out x in external clock open external oscillator crystal or ceramic oscillator 8mhz crystal oscillator x out x in
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 73 20. reset the gms815xxb have two types of reset generation pro- cedures; one is an external reset input, the other is a watch- dog timer reset. table 20-1 shows on-chip hardware ini- tialization by reset action. table 20-1 initializing internal status by reset action 20.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start ex- ecution as shown in figure 20-2. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at addresses fffe h - ffff h . a connection for simple power-on-reset is shown in figure 20-1. figure 20-1 simple power-on-reset circuit figure 20-2 timing diagram after reset 20.2 watchdog timer reset refer to 17. watchdog timer on page 67. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) watchdog timer disable g-flag (g) 0 control registers refer to table 8-1 on page 28 peripheral clock off power fail detector disable 7036p v cc 10uf + 10k w to the reset pin main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1
gms81508b/16b/24b, gms82512/16/24 74 may. 2001 ver 2.0 21. power fail processor the gms815xxb and gms825xx have an on-chip power fail detection circuitry to immunize against power noise. a configuration register, pfdr, can enable or disable the power fail detect circuitry. whenever v dd falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze mcu according to pfr bit of pfdr. refer to 7.4 dc electrical characteristics on page 16. in the in-circuit emulator, power fail function is not imple- mented and user can not experiment with it. therefore, af- ter final development of user program, this function may be experimented or evaluated. note: user can select power fail voltage level according to pfv bit of pfdr at the otp(gms815xxbt/gms825xxt) but must select the power fail voltage level to define pfd option of mask order & verification sheet at the mask chip(gms815xxb/gms825xx). because the power fail voltage level of mask chip (gms815xxb/gms825xx) is determined according to mask option regardless of pfv bit of pfdr note: if power fail voltage is selected to 3.0v on 3v oper- ation, mcu is freezed at all the times. table 21-1 power fail processor figure 21-1 power fail voltage detector register power failfunction otp mask enable/disable by pfd flag by pfd flag level selection by pfv flag by mask option 76543210 pfs initial value: ---- 1100 b address: 0f9 h pfdr r/w r/w r/w pfd operation mode 0: normal operation regardless of power fail 1: mcu will be reset by power fail detection disable flag 0: power fail detection enable 1: power fail detection disable power fail status 0: normal operate 1: set to 1 if power fail is detected pfr pfv power fail voltage selection flag 0: 2.4v 1: 3.0v r/w
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 75 figure 21-2 example s/w of reset flow by power fail figure 21-3 power fail processor situations funtion execution initialize ram data pfs =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine pfs = 0 internal reset internal reset internal reset v dd v dd v dd v pfd max v pfd min v pfd max v pfd min v pfd max v pfd min 64ms 64ms t <64ms 64ms when pfr = 1
gms81508b/16b/24b, gms82512/16/24 76 may. 2001 ver 2.0 22. otp programming the gms81516bt/24bt and gms82524t are otp (one time programmable) microcontrollers. its internal user memory is constructed with eprom (electrically pro- grammable read only memory). the otp micorcontroller is generally used for chip evalu- ation, first production, small amount production, fast mass production, etc. blank otps internal eprom is filled by 00 h , not ff h . note: in any case, you have to use *.otp file, not *.hex file. after assemble, both otp and hex file are generated by automatically. the hex file is used during porgram em- ulation on emulator. 22.1 how to program to program the otp devices, user can use hynix own pro- grammer or third party universal programmer shown as listed below. hynix own programmer list manufacturer: hynix semiconductor inc. programmer: choice-sigma, stand-alone gang4 choice-sigma is a hynix universal single programmer for any hynix otp devices, and the stand-alone gang4 can program four otps at once. ask to hynix sales part which is listed on appendix of this manual for purchasing or more detail. third party programmer list manufacturer: hi-lo systems programmer: all-11 website : http: //www.hilosystems.com.tw * all-07 : even though hilo system does not support all07 any longer, user can get the specific program algo- rithm and socket adapter for all-07 from hynix sales part. ( file name : ampu7.exe ) programming procedure 1. select device gms81516bt or gms81524bt or gms82524t as you want. 2. load the *.otp file to the programmer. the file is com- posed of motorola-s1 format. 3. set the programming address range as below table. 4. mount the socket adapter on the programmer. 5. start program/verify. 22.2 pin function v pp (program voltage) v pp is the input for the program voltage for programming the eprom. ce (chip enable) ce is the input for programming and verifying internal eprom. oe (output enable) oe is the input of data output control signal for verify. a0~a15 (address bus) a0~a15 are address input pins for internal eprom. o0~o7 (eprom data bus) these are data bus for internal eprom. gms81516bt address set value bufferstart address 4000h buffer end address 7fffh device start address c000h gms81524bt, gms82524t address set value bufferstart address 2000h buffer end address 7fffh device start address a000h
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 77 table 22-1 socket adapter pin assignment for gms81516bt/24bt v dd v pp o0 o1 o2 o3 o4 o5 o6 o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 64sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gms81516bt/24bt v dd ce oe open gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 64mqfp gms815016bt/24bt o0 o1 o2 o3 o4 o5 o6 o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 open gnd gnd v dd v pp ce oe v dd
gms81508b/16b/24b, gms82512/16/24 78 may. 2001 ver 2.0 table 22-2 socket adapter pin assignment for gms81516bt/24bt o0 o1 o2 o3 o4 o5 o6 o7 a0 a1 a2 a3 a4 a5 a6 a7 gnd v dd v pp ce oe v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 gms81516bt/24bt 64lqfp a8 a9 a10 a11 a12 a13 a14 a15 open
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 79 table 22-3 socket adapter pin assignment for gms82524t a1 a2 a3 a4 a5 a6 a7 o0 o1 o2 o3 o4 o5 o6 o7 a8 a9 a10 a11 a12 a13 42sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 gms82524t (top view) a0 v dd v pp gnd ce oe n.c. * a15 a14 (top view) a9 a10 a11 a12 a13 a14 a15 a7 o0 o1 o2 o3 o4 o5 o6 o7 n.c. a8 1 2 3 4 5 6 7 8 9 10 11 a6 a5 a4 a3 a2 a1 a0 v dd 33 32 31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 gms82524t 44qfp 18 19 20 21 22 n.c. * v pp ce oe v dd n.c. * n.c. * : no connection
gms81508b/16b/24b, gms82512/16/24 80 may. 2001 ver 2.0 22.3 programming specification device operation mode (t a = 25 c 5 c) device characteristics (v ss =0v, t a = 25 c 5 c) mode ce oe a0~a15 v pp v dd o0~o7 read mode x 1 x 1 v dd 2 5.0v dout output disable mode v ih v ih x 1 v dd 2 5.0v hi-z programming mode v il v ih x 1 v pp 2 v dd 2 din program verify x 1 x 1 v pp 2 v dd 2 dout 1. x = either v il or v ih . 2. see dc characteristics table for v dd and v pp voltage during programming. symbol item min typ max unit test condition v pp quick pulse programming 11.50 11.75 12.0 v v dd 1 quick pulse programming 5.75 6.0 6.25 v i pp 2 v pp supply current 50 ma ce =v il i dd 2 v dd supply current 30 ma v ih input high voltage 0.8v dd v v il input low voltage 0.2v dd v v oh output high voltage v dd -0.1 v i oh = -2.5ma v ol output low voltage 0.4 v i ol = 2.1ma i il input leakage current 5 m a 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the maximum current value is with outputs o0 to o7 unloaded.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 81 switching waveforms reading waveforms 1. the input timing reference level is 1.0v for a v il and 4.0v for a v ih at v dd =5.0v. 2. to read the output data, transition requires on the oe form the high to the low after address setup time t as . waveform must be steady inputs outputs will be steady may change will be changing from h to l from h to l may change will be changing from l to h from l to h do not care any changing state change permitted unknown does not apply center line is high impedance off state addresses valid addresses valid output v ih v il v ih v il v ih v il oe output t as t oe t dh high-z see note (2)
gms81508b/16b/24b, gms82512/16/24 82 may. 2001 ver 2.0 programming algorithm waveforms 1. the input timing reference level is 1.0v for a v il and 4.0v for a v ih at v dd =5.0v. addresses valid addresses v ih v il t dh high-z t ah t dfp program program verify data in/out v pp v dd ce oe t as t ds t vps t vds t pw data in stable data out valid t oes t oe v ih v il 12.75v v dd 6.25v 5.0v v ih v il v ih v il
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 83 ac reading characteristics (v ss =0v, t a = 25 c 5 c) note: v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . ac programming characteristics (v ss =0v, t a = 25 c 5 c) * ac condition of test input rise and fall times (10% to 90%) ........................... 20ns input pulse levels ............................................................. 0.45v to 4.55v input timing reference level............................................ 1.0v to 4.0v output timing reference level ......................................... 1.0v to 4.0v v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . symbol item min typ max unit test condition t as address setup time 2 m s t oe quick pulse programming 200 ns t dh v pp supply current 050ns symbol item min typ max unit test condition* t as address setup time 2 m s t oes oe setup time 2 m s t ds data setup time 2 m s t ah address hold time 0 m s t dh data hold time 2 m s t dfp output delay disable time 0 130 ns t vps v pp setup time 2 m s t vds v dd setup time 2 m s t pw program pulse width 95 100 105 m s t oe data output delay time 150 ns
gms81508b/16b/24b, gms82512/16/24 84 may. 2001 ver 2.0 table 22-4 programming algorithm start address=first location v cc =6.0v v pp =11.75 x=0 program one 100 m s pulse increment x x=25? no yes verify one byte last address? v cc =v pp =5.0v compare all bytes to original data device failed device passed verify byte increment address no yes fail pass fail pass fail pass
appendix
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 i a. control register list address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w undefined 34 00c1 r0 port i/o direction register r0dd w 0 0 0 0 0 0 0 0 34 * 00c2 r1 port data register r1 r/w undefined 34 * 00c3 r1 port i/o direction register r1dd w 0 0 0 0 0 0 0 0 34 00c4 r2 port data register r2 r/w undefined 34 00c5 r2 port i/o direction register r2dd w 0 0 0 0 0 0 0 0 34 00c6 r3 port data register r3 r/w undefined 34 00c7 r3 port i/o direction register r3dd w 0 0 0 0 0 0 0 0 34 00c8 r4 port data register r4 r/w undefined 34 00c9 r4 port i/o direction register r4dd w 0 0 0 0 0 0 0 0 34 00ca r5 port data register r5 r/w undefined 34 00cb r5 port i/o direction register r5dd w 0 0 0 0 0 0 0 0 34 00cc r6 port data register r6 r/w undefined 34 00cd r6 port i/o direction register r6dd w 0 0 0 0 - - - - 34 00d0 r4 port mode register pmr4 w 0 0 0 0 0 0 0 0 34, 66 00d1 r5 port mode register pmr5 w - - 0 0 - - - - 34, 58 00d3 basic interval timer mode register bitr r undefined 37 clock control register ckctlr w - - 0 1 0 1 1 1 37 00e0 watchdog timer register wdtr w - 0 1 1 1 1 1 1 67 00e2 timer mode register 0 tm0 r/w 0 0 0 0 0 0 0 0 39 00e3 timer mode register 2 tm2 r/w 0 0 0 0 0 0 0 0 39 00e4 timer 0 data register tdr0 w undefined 39 timer 0 counter register t0 r undefined 39 00e5 timer 1 data register tdr1 w undefined 39 timer 1 counter register t1 r undefined 39 00e6 timer 2 data register tdr2 w undefined 39 timer 2 counter register t2 r undefined 39 00e7 timer 3 data register tdr3 w undefined 39 timer 3 counter register t3 r undefined 39 00e8 a/d converter mode register adcm r/w - - 0 0 0 0 0 1 49 00e9 a/d converter data register adr r undefined 49 * 00ea serial i/o mode register siom r/w - 0 0 0 0 0 0 1 51 * 00eb serial i/o register sior r/w undefined 51 00ec buzzer driver register bur w undefined 58 * 00f0 pwm0 duty register pwmr0 w undefined 55 * 00f1 pwm1 duty register pwmr1 w undefined 55
gms81508b/16b/24b, gms82512/16/24 ii may. 2001 ver 2.0 * 00f2 pwm control register pwmcr w 0 0 0 0 0 0 0 0 55 00f4 interrupt enable register low ienl r/w 0 0 0 0 - - - - 60 00f5 interrupt request flag register low irql r/w 0 0 0 0 - - - - 60 00f6 interrupt enable register high ienh r/w 0 0 0 0 0 0 0 0 60 00f7 interrupt request flag register high irqh r/w 0 0 0 0 0 0 0 0 60 00f8 external interrupt edge selection register ieds w 0 0 0 0 0 0 0 0 60 00f9 power fail detection register pfdr r/w - - - - 1 1 0 0 74 address register name symbol r/w initial value page 76543210 registers are controlled by byte manipulation instruction such as ldm etc., do not use bit manipulation w registers are controlled by both bit and byte manipulation instruction. r/w instruction such as set1, clr1 etc. if bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved. * : this bit is not served on gms825xx.
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 iii b. software example b.1 7-segment led display ;***************************************************************************** ; title: gms81516bt (gms800 series) demonstration program * ; company: hynix semiconductor * ; contents: decimal up/down counter * ; programmer: hynix mcu application team * ;***************************************************************************** ; ;******** define i/o port & function register address ********* ; r0 equ 0c0h ;port r0 register r0dd equ 0c1h ;port r0 data i/o direction register ; r1 equ 0c2h ;port r1 register r1dd equ 0c3h ;port r1 data i/o direction register ; r2 equ 0c4h ;port r2 register r2dd equ 0c5h ;port r2 data i/o direction register ; r3 equ 0c6h ;port r3 register r3dd equ 0c7h ;port r3 data i/o direction register ; r4 equ 0c8h ;port r4 register r4dd equ 0c9h ;port r4 data i/o direction register ; r5 equ 0cah ;port r5 register r5dd equ 0cbh ;port r5 data i/o direction register ; r6 equ 0cch ;port r6 register r6dd equ 0cdh ;port r6 data i/o direction register ; pmr4 equ 0d0h ;port r4 mode register t3s equ 7,0d0h ;timer3 selection gms81516bt led display gnd r00 r01 r02 r03 r04 r05 r06 a b c d e f g 330 w 7 4.7k w 4.7k w r23 r22 r20/int0 r21/int1 up/down s/w clear s/w 2n2222 2n2222
gms81508b/16b/24b, gms82512/16/24 iv may. 2001 ver 2.0 t1s equ 6,0d0h ;timer1 selection ec2s equ 5,0d0h ;event counter 2 selection ec0s equ 4,0d0h ;event counter 0 selection int3s equ 3,0d0h ;external int.3 selection int2s equ 2,0d0h ;external int.2 selection int1s equ 1,0d0h ;external int.1 selection int0s equ 0,0d0h ;external int.0 selection ; pmr5 equ 0d1h ;port r5 mode register buzs equ 5,0d1h ;buzzer selection wdts equ 4,0d1h ;watch dog timer selection ; tmr equ 0d2h ;test mode register ; ckctlr equ 0d3h ;clock control register bitr equ 0d3h ;basic interval timer register ; ;wdtr equ 0e0h ;watch dog timer register ; tm0 equ 0e2h ;timer0 mode register tm2 equ 0e3h ;timer2 mode register ; tdr0 equ 0e4h ;tomer0 data register tdr1 equ 0e5h ;tomer1 data register tdr2 equ 0e6h ;tomer2 data register tdr3 equ 0e7h ;tomer3 data register ; adcm equ 0e8h ;a/d converter mode register adr equ 0e9h ;a/d con. register ; siom equ 0eah ;serial i/o mode register ;sior equ 0ebh ;serial i/o register ; bur equ 0ech ;buzzer data register ; pwmr0 equ 0f0h ;pwm0 data register pwmr1 equ 0f1h ;pwm1 data register ; pwmcr equ 0f2h ;pwm control register ; imod equ 0f3h ;interrupt mode register ienl equ 0f4h ;int. enable register low ae equ 7,0f4h ;a/d con. int. enable wdte equ 6,0f4h ;w.d.t. int. enable bite equ 5,0f4h ;b.i.t. int. enable se equ 4,0f4h ;serial i/o int. enable ; irql equ 0f5h ;int. request flag register low ar equ 7,0f5h ;a/d con. int. request flag wdtrf equ 6,0f5h ;w.d.t. int. request flag bitrf equ 5,0f5h ;b.i.t. int. request flag sr equ 4,0f5h ;serial i/o int. request flag ; ienh equ 0f6h ;int. enable register high int0e equ 7,0f6h ;external int.0 enable int1e equ 6,0f6h ;external int.1 enable int2e equ 5,0f6h ;external int.2 enable int3e equ 4,0f6h ;external int.3 enable t0e equ 3,0f6h ;timer0 int. enable t1e equ 2,0f6h ;timer1 int. enable t2e equ 1,0f6h ;timer2 int. enable t3e equ 0,0f6h ;timer3 int. enable ; irqh equ 0f7h ;int. request flag register high int0r equ 7,0f7h ;external int.0 request flag int1r equ 6,0f7h ;external int.1 request flag int2r equ 5,0f7h ;external int.2 request flag int3r equ 4,0f7h ;external int.3 request flag t0r equ 3,0f7h ;timer0 int. request flag t1r equ 2,0f7h ;timer1 int. request flag t2r equ 1,0f7h ;timer2 int. request flag t3r equ 0,0f7h ;timer3 int. request flag ; ieds equ 0f8h ;external int. edge selection ; ;*********** macro definition ************ ; reg_save macro ;save registers to stacks push a push x
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 v push y endm ; reg_restore macro ;restore register from stacks pop y pop x pop a endm ; ;*********** constant definition *********** ; seg_port equ r0 ;7-segment output port strobe_port equ r2 ;strobe signal port ; ;************************************************************************** ; ram allocation * ;************************************************************************** digit10 ds 1 ;dig10 display data digit1 ds 1 ;seg1 display data strobe ds 1 ;strobe signal data tmr_500ms ds 1 ;500ms time counter flags ds 1 ;function flags up_f equ 0,flags ;1=down,0=up f_500ms equ 1,flags ; ; ;************************************************************************** ; interrupt vector table * ;************************************************************************** ; org0ffe4h dw not_used ; serial i/o dw not_used ; basic interval timer dw not_used ; watch dog timer dw not_used ; a/d con. dw not_used ; timer-3 dw not_used ; timer-2 dw not_used ; timer-1 dw tmr0_int ; timer-0 dw not_used ; int.3 dw not_used ; int.2 dw int_1 ; int.1 dw int_0 ; int.0 dw not_used ; dw reset ; reset ; ;************************************************************************** ; main program * ;************************************************************************** ; org 0c000h ;program start address ; reset: di ;disable all interrupts ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ ;m(x) <- a, then x <- x+1 cmpx #0c0h ;x = #0c0h ? bne ram_clr ; ldx #0feh ;stack pointer initial txsp ;sp. <- #0feh ldm r0,#0 ;i/o port data clear ldm r2,#0 ldm r0dd,#0ffh ;7-seg. data output mode ldm r2dd,#00fh ;7-seg. strobe output mode ldm strobe,#0000_1011b ldm tdr0,#250 ;8us x 250 = 2000us ldm tm0,#0001_1111b ;timer0(8bit),8us,start count-up ldm irqh,#0 ;clear all interrupts requeat flags ldm irql,#0 ldm ienh,#1100_1000b ;enablet0,int0,int1,interrupt ldm ienl,#00h ldm ieds,#0101_0101b ;external int. falling edge select ldm pmr4,#03h ;general port or int? set1 up_f ei ;enable interrupts
gms81508b/16b/24b, gms82512/16/24 vi may. 2001 ver 2.0 ; loop: nop if f_500ms == 1 clr1 f_500ms call inc_dec endif jmp loop ; ;*********************************************** ; subject: inc. or dec. two digits * ;*********************************************** ; entry: up_f * ; return: up_f=1, increment two digits * ; up_f=0, decrement two digits * ;*********************************************** ; inc_dec: bbc up_f,down ;check down mode or up mode ; ;************************** ;* up count * ;************************** ; setc lda #0 ; digit1 <- digit1 + 1 adc digit1 if a == #0ah setc lda #0 endif sta digit1 ; store result into digit1 ; lda #0 ; when overflow is set, adc digit10 ; digit10 <- digit10 + 1 if a == #10 lda #0 endif sta digit10 ret ; ;************************** ;* down count * ;************************** ; down: clrc lda digit1 ; digit1 <- digit1 - 1 sbc #0 if a == #0ffh lda #9 clrc else setc endif sta digit1 ; store result into digit1 ; lda digit10 ; when overflow is set, sbc #0 ; digit10 <- digit10 - 1 if a == #0ffh lda #9 endif sta digit10 ret ; ;************************************************************************** ; timer0,interrupt routine(2ms)& int0,int1 * ;************************************************************************** ; tmr0_int: reg_save ;save registers to stacks call dsply ;segments data port output call make_500msfalg ;250ms mesurement reg_restore ;restore registers from stacks reti ; ;************************************************************************** ; external interrupt 0 (up/down key) * ;************************************************************************** ; int_0: not1 up_f ;int0 service routine reti ;toggle the up/down mode ;
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 vii ;************************************************************************** ; external interrupt 1 (clear key) * ;************************************************************************** ; int_1: ldm digit1,#0 ;int1 service routine ldm digit10,#0 ldm tmr_500ms,#0 ;0.5sec restart reti ; ;*********************************************************************** ; subject: seven segment display (dsply) * ;*********************************************************************** ; entry: digit10 or digit1 * ; return: output seg_port (r00~r07), * ; strobe_port (r22,r23) * ; scratch: strobe * ;*********************************************************************** ; description: after read internal ram data, output data to the port * ;*********************************************************************** ; dsply: ldm strobe_port,#03h ;segment all turn off not1 strobe.2 ;toggle strobe0 not1 strobe.3 ;toggle strobe1 if strobe.3 = 1 ;test if r23 is high. ldy digit1 else ldy digit10 endif lda !font+y sta seg_port ;segment data output lda strobe sta strobe_port ;current digit turn on ret ;quit ; ;*********************************************** ; subject: set falg at every 500ms * ;*********************************************** ; entry: none * ; return: 500ms flag (f_500ms) * ;*********************************************** ; make_500msfalg: inc tmr_500ms ;count up every 2ms lda tmr_500ms if a == #250 ;compare 0.5s ldm tmr_500ms,#0 ;clear 0.5sec. counter set1 f_500ms ;set 0.5sec. flag endif ret ; ;************************************************************************** ; 7-segment pattern data * ; _a_ * ; f | g |b * ; |---| * ; e |___|c * ; d .h * ;************************************************************************** ; segment: hgfe dcba to be displayed digit number font db 0011_1111b ; 0 db 0000_0110b ; 1 db 0101_1011b ; 2 db 0100_1111b ; 3 db 0110_0110b ; 4 db 0110_1101b ; 5 db 0111_1100b ; 6 db 0000_0111b ; 7 db 0111_1111b ; 8 db 0110_0111b ; 9 ; ;************************************************************************** ; not_used: nop ;discard unexpected interrupts reti ; end ;notice program end
gms81508b/16b/24b, gms82512/16/24 viii may. 2001 ver 2.0 c. instruction c.1 terminology list terminology description a a - register x x - register y y - register psw program status word c carry flag of psw v overflow flag of psw n negative flag of psw i master interrupt enable flag of psw z zero flag of psw h half carry flag of psw b break flag of psw (software interrupt) g g flag of psw(direct page) pc program counter sp stack pointer #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect address { } register indirect address { }+ register indirect address, register auto-increment .bit bit position a.bit bit position of a-register dp.bit bit position of direct page memory m.bit bit position of memory (000 h ~ 0fff h ) rel relative addressing data upage u - page(0ff00 h ~ 0ffff h ) offset address n table call number (0 ~ 15) x indicate upper nibble of op code y indicate upper nibble of op code ? assignment / transfer / shift left ? shift right ? exchange h,h hexadecimal b,b binary + addition x multiplication = equal logical and ? exclusive or d,d decimal ( ) contents of - subtraction ? division 1 not equal logical or (overline) logical not bit position 0 bit position 1
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 ix c.2 instruction map /2: 33333 33 33334 34 33343 35 33344 36 33433 37 33434 38 33443 39 33444 3: 34333 3; 34334 3< 34343 3 $ 34344 3 % 34433 3 & 34434 3 ' 34443 3 ( 34444 3 ) +,*+ 333 0 6(7 4 gs 1 elw %%6 $ 1 elw / uho %%6 gs 1 elw / uho $'& & lpp $'& gs $'& gs . ; $'& $ dev $6/ $ $6/ gs 7&$// 3 6(7$ 4 1 elw %,7 gs 323 $ 386+ $ %5. 334 &/5& 22 22 22 6%& & lpp 6%& gs 6%& gs . ; 6%& $ dev 52/ $ 52/ gs 7&$// 5 &/5$ 4 1 elw &20 gs 323 ; 386+ ; %5$ uho 343 &/5* 22 22 22 &03 & lpp &03 gs &03 gs . ; &03 $ dev /65 $ /65 gs 7&$// 7 127 4 0 1 elw 767 gs 323 < 386+ < 3&$// 8sdjh 344 ', 22 22 22 25 & lpp 25 gs 25 gs . ; 25 $ dev 525 $ 525 gs 7&$// 9 25 4 25 4 % &03; gs 323 36: 386+ 36: 5(7 433 &/59 22 22 22 $1' & lpp $1' gs $1' gs . ; $1' $ dev ,1& $ ,1& gs 7&$// ; $1' 4 $1' 4 % &03< gs &%1( gs . ; 7;63 ,1& ; 434 6(7& 22 22 22 (25 & lpp (25 gs (25 gs . ; (25 $ dev '(& $ '(& gs 7&$// 43 (25 4 (25 4 % '%1( gs ;0$ gs . ; 763; '(& ; 443 6(7* 22 22 22 /'$ & lpp /'$ gs /'$ gs . ; /'$ $ dev 7;$ /'< gs 7&$// 45 /'& /'&% /'; gs /'; gs . < ;&1 '$6 444 (, 22 22 22 /'0 gs /& lpp 67$ gs 67$ gs . ; 67$ $ dev 7$; 67< gs 7&$// 47 67& 0 1 elw 67; gs 67; gs . < ;$6 6723 4 1. stop instruction is expressed to 00 h to hex file(filename.hex) which is loaded into mds with eva815/816/825xx board. /2: 43333 43 43334 44 43343 45 43344 46 43433 47 43434 48 43443 49 43444 4: 44333 4; 44334 4< 44343 4 $ 44344 4 % 44433 4 & 44434 4 ' 44443 4 ( 44444 4 ) +,*+ 333 %3/ uho &/5 4 gs 1 elw %%& $ 1 elw / uho %%& gs 1 elw / uho $'& ^;` $'& $ dev . < $'& >gs . ;@ $'& >gs@ . < $6/ $ dev $6/ gs . ; 7&$// 4 -03 $ dev %,7 $ dev $'': gs /'; & lpp -03 > $ dev@ 334 %9& uho 22 22 22 6%& ^;` 6%& $ dev . < 6%& >gs . ;@ 6%& >gs@ . < 52/ $ dev 52/ gs . ; 7&$// 6 &$// $ dev 7(67 $ dev 68%: gs /'< & lpp -03 >gs@ 343 %&& uho 22 22 22 &03 ^;` &03 $ dev . < &03 >gs . ;@ &03 >gs@ . < /65 $ dev /65 gs . ; 7&$// 8 08/ 7&/5 4 $ dev &03: gs &03; & lpp &$// >gs@ 344 %1( uho 22 22 22 25 ^;` 25 $ dev . < 25 >gs . ;@ 25 >gs@ . < 525 $ dev 525 gs . ; 7&$// : '%1( < &03; $ dev /'<$ gs &03< & lpp 5(7, 433 %0, uho 22 22 22 $1' ^;` $1' $ dev . < $1' >gs . ;@ $1' >gs@ . < ,1& $ dev ,1& gs . ; 7&$// < ',9 &03< $ dev ,1&: gs ,1& < 7$< 434 %96 uho 22 22 22 (25 ^;` (25 $ dev . < (25 >gs . ;@ (25 >gs@ . < '(& $ dev '(& gs . ; 7&$// 44 ;0$ ^;` ;0$ gs '(&: gs '(& < 7<$ 443 %&6 uho 22 22 22 /'$ ^;` /'$ $ dev . < /'$ >gs . ;@ /'$ >gs@ . < /'< $ dev /'< gs . ; 7&$// 46 /'$ ^;` . /'; $ dev 67<$ gs ;$< '$$ 444 %(4 uho 22 22 22 67$ ^;` 67$ $ dev . < 67$ >gs . ;@ 67$ >gs@ . < 67< $ dev 67< gs . ; 7&$// 48 67$ ^;` . 67; $ dev &%1( gs ;<; 123
gms81508b/16b/24b, gms82512/16/24 x may. 2001 ver 2.0 c.3 alphabetic order table of instruction no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 10 and #imm 84 2 2 logical and n - - - - - z - 11 and dp 85 2 3 a ? a (m) 12 and dp + x 86 2 4 13 and !abs 87 3 4 14 and !abs+y 95 3 5 15 and [dp+x] 96 2 6 16 and [dp] + y 97 2 6 17 and {x} 94 1 3 18 and1 m.bit 8b 3 4 bit and c-flag : c ? c (m.bit) - - - - - - - c 19 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c (m.bit) - - - - - - - c 20 asl a 08 1 2 arithmetic shift left n - - - - - zc 21 asl dp 09 2 4 22 asl dp + x 19 2 5 23 asl !abs 18 3 5 24 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 25 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 26 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 27 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 28 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 29 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 30 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 31 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 32 bit !abs 1c 3 5 z ? a m, n ? (m 7 ), v ? (m 6 ) 33 bmi rel 90 2 2/4 branch if munus : if (n) = 1, then pc ? pc + rel - - - - - - - - 34 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 35 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 36 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 37 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 38 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 39 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel 40 call !abs 3b 3 8 subroutine call - - - - - - - - 41 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 xi 42 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 43 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 44 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 45 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 46 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 47 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - 48 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 49 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 50 cmp dp 45 2 3 a - (m) 51 cmp dp + x 46 2 4 52 cmp !abs 47 3 4 53 cmp !abs + y 55 3 5 54 cmp [dp + x] 56 2 6 55 cmp [dp] + y 57 2 6 56 cmp {x} 54 1 3 57 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 58 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 59 cmpx dp 6c 2 3 x - (m) 60 cmpx !abs 7c 3 4 61 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 62 cmpy dp 8c 2 3 y - (m) 63 cmpy !abs 9c 3 4 64 com dp 2c 2 4 1s complement : (dp) ? (dp) n - - - - - z - 65 daa df 1 3 decimal adjust for addition n - - - - - zc 66 das cf 1 3 decimal adjust for substraction n - - - - - zc 67 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 68 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 69 dec a a8 1 2 decrement n - - - - - z - 70 dec dp a9 2 4 m ? m - 1 71 dec dp + x b9 2 5 72 dec !abs b8 3 5 73 dec x af 1 2 74 dec y be 1 2 75 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 76 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 77 div 9b 1 12 divide : ya ? a ? q:a, r:y nv - - h - z - 78 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 79 eor #imm a4 2 2 exclusive or n - - - - - z - 80 eor dp a5 2 3 a ? a ? (m) 81 eor dp + x a6 2 4 82 eor !abs a7 3 4 83 eor !abs + y b5 3 5 84 eor [ dp + x] 96 2 6 85 eor [dp] + y 97 2 6 86 eor {x} 94 1 3 87 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 88 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? (m.bit) - - - - - - - c 89 inc a 88 1 2 increment n - - - - - zc no. mnenonic op code byte no. cycle no operation flag nvgbhizc
gms81508b/16b/24b, gms82512/16/24 xii may. 2001 ver 2.0 90 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 91 inc dp + x 99 2 5 92 inc !abs 98 3 5 93 inc x 8f 1 2 94 inc y 9e 1 2 95 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z - 96 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 97 jmp [!abs] 1f 3 5 pc ? jump address 98 jmp [dp] 3f 2 4 99 lda #imm c4 2 2 load accumulator n - - - - - z - 100 lda dp c5 2 3 a ? (m) 101 lda dp + x c6 2 4 102 lda !abs c7 3 4 103 lda !abs + y d5 3 5 104 lda [dp + x] d6 2 6 105 lda [dp]+y d7 2 6 106 lda {x} d4 1 3 107 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 108 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 109 ldcb m.bit cb 3 4 load c-flag with not : c ? (m.bit) - - - - - - - c 110 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 111 ldx #imm 1e 2 2 load x-register n - - - - - z - 112 ldx dp cc 2 3 x ? (m) 113 ldx dp + y cd 2 4 114 ldx !abs dc 3 4 115 ldy #imm 3e 2 2 load x-register n - - - - - z - 116 ldy dp c9 2 3 y ? (m) 117 ldy dp + y d9 2 4 118 ldy !abs d8 3 4 119 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 120 lsr a 48 1 2 logical shift right n - - - - - zc 121 lsr dp 49 2 4 122 lsr dp + x 59 2 5 123 lsr !abs 58 3 5 124 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 125 nop ff 1 2 no operation - - - - - - - - 126 not1 m.bit 4b 3 5 bit complement : (m.bit) ? (m.bit) - - - - - - - - 127 or #imm 64 2 2 logical or n - - - - - z - 128 or dp 65 2 3 a ? a v (m) 129 or dp + x 66 2 4 130 or !abs 67 3 4 131 or !abs + y 75 3 5 132 or [dp +x} 76 2 6 133 or [dp] + y 77 2 6 134 or {x} 74 1 3 135 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 136 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v (m.bit) - - - - - - - c 137 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ?
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 xiii 138 pop a 0d 1 4 pop from stack - - - - - - - - 139 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 140 pop y 4d 1 4 141 pop psw 6d 1 4 (restored) 142 push a 0e 1 4 push to stack - - - - - - - - 143 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 144 push y 4e 1 4 145 push psw 6e 1 4 146 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 147 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 148 rol a 28 1 2 rotate left through carry n - - - - - zc 149 rol dp 29 2 4 150 rol dp + x 39 2 5 151 rol !abs 38 3 5 152 ror a 68 1 2 rotate right through carry n - - - - - zc 153 ror dp 69 2 4 154 ror dp + x 79 2 5 155 ror !abs 78 3 5 156 sbc #imm 24 2 2 subtract with carry nv - - hzc 157 sbc dp 25 2 3 a ? a - (m) - (c) 158 sbc dp + x 26 2 4 159 sbc !abs 27 3 4 160 sbc !abs + y 35 3 5 161 sbc [dp + x] 36 2 6 162 sbc [dp] + y 37 2 6 163 sbc {x} 34 1 3 164 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 165 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 166 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 167 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 168 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 169 sta dp + x e6 2 4 (m) ? a 170 sta !abs e7 3 4 171 sta !abs + y f5 3 5 172 sta [dp + x] f6 2 6 173 sta [dp] + y f7 2 6 174 sta {x} f4 1 3 175 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 176 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 177 stop ef 1 3 stop mode (halt cpu, stop oscillator) - - - - - - - - 178 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 179 stx dp + y ed 2 5 (m) ? x 180 stx !abs fc 3 5 181 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 182 sty dp + x f9 2 5 (m) ? y 183 sty !abs f8 3 5 184 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 185 subw dp 3d 2 5 16-bits subtract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc no. mnenonic op code byte no. cycle no operation flag nvgbhizc c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
gms81508b/16b/24b, gms82512/16/24 xiv may. 2001 ver 2.0 186 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 187 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 188 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h) 189 tclr1 !abs 5c 3 6 test and clear bits with a : a - (m), (m) ? (m) (a) n - - - - - z - 190 tset1 !abs 3c 3 6 test and set bits with a : a - (m), (m) ? (m) v (a) n - - - - - z - 191 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 192 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 193 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 194 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 195 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 196 xax ee 1 4 exchange x-register contents with accumulator : x ? a - - - - - - - - 197 xay de 1 4 exchange y-register contents with accumulator : y ? a - - - - - - - - 198 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 ? a 3 ~ a 0 199 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 200 xma dp + x ad 2 6 (m) ? a 201 xma {x} bb 1 5 202 xyx fe 1 4 exchange x-register contents with y-register : x ? y - - - - - - - - no. mnenonic op code byte no. cycle no operation flag nvgbhizc
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 xv c.4 instruction table by function arithmetic/logic operation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. nv - - h - zc 2 adc dp 05 2 3 a ? a + (m) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs+y 15 3 5 6 adc [dp+x] 16 2 6 7 adc [dp]+y 17 2 6 8 adc {x} 14 1 3 9 and #imm 84 2 2 logical and n - - - - - z - 10 and dp 85 2 3 a ? a (m) 11 and dp + x 86 2 4 12 and !abs 87 3 4 13 and !abs+y 95 3 5 14 and [dp+x] 96 2 6 15 and [dp] + y 97 2 6 16 and {x} 94 1 3 17 asl a 08 1 2 arithmetic shift left n - - - - - zc 18 asl dp 09 2 4 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents n - - - - - zc 22 cmp dp 45 2 3 a - (m) 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 25 cmp !abs + y 55 3 5 26 cmp [dp + x] 56 2 6 27 cmp [dp] + y 57 2 6 28 cmp {x} 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents n - - - - - zc 30 cmpx dp 6c 2 3 x - (m) 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents n - - - - - zc 33 cmpy dp 8c 2 3 y - (m) 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : (dp) ? (dp) n - - - - - z - 36 daa df 1 3 decimal adjust for addition n - - - - - zc 37 das cf 1 3 decimal adjust for subtraction n - - - - - zc 38 dec a a8 1 2 decrement n - - - - - z - 39 dec dp a9 2 4 m ? m - 1 40 dec dp + x b9 2 5 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 44 div 9b 1 12 divide : ya ? a ? q:a, r:y nv - - h - z - c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? " 0 "
gms81508b/16b/24b, gms82512/16/24 xvi may. 2001 ver 2.0 45 eor #imm a4 2 2 exclusive or n - - - - - z - 46 eor dp a5 2 3 a ? a ? (m) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 49 eor !abs + y b5 3 5 50 eor [ dp + x] 96 2 6 51 eor [dp] + y 97 2 6 52 eor {x} 94 1 3 53 inc a 88 1 2 increment n - - - - - zc 54 inc dp 89 2 4 (m) ? (m) + 1 n - - - - - z - 55 inc dp + x 99 2 5 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 logical shift right n - - - - - zc 60 lsr dp 49 2 4 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y x a n - - - - - z - 64 or #imm 64 2 2 logical or n - - - - - z - 65 or dp 65 2 3 a ? a v (m) 66 or dp + x 66 2 4 67 or !abs 67 3 4 68 or !abs + y 75 3 5 69 or [dp +x} 76 2 6 70 or [dp] + y 77 2 6 71 or {x} 74 1 3 72 rol a 28 1 2 rotate left through carry n - - - - - zc 73 rol dp 29 2 4 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry n - - - - - zc 77 ror dp 69 2 4 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry nv - - hzc 81 sbc dp 25 2 3 a ? a - (m) - (c) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 84 sbc !abs + y 35 3 5 85 sbc [dp + x] 36 2 6 86 sbc [dp] + y 37 2 6 87 sbc {x} 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero : (dp) - 00 h n - - - - - z - 89 xcn ce 1 5 exchange nibbles within the accumulator: n - - - - - z - a 7 ~ a 4 ? a 3 ~ a 0 no. mnenonic op code byte no. cycle no operation flag nvgbhizc 7 6 5 4 3 2 1 0 c " 0 " ? ? ? ? ? ? ? ? ? ? c 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 c ? ? ? ? ? ? ? ? ?
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 xvii register / memory operation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator n - - - - - z - 2 lda dp c5 2 3 a ? (m) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 6 lda [dp + x] d6 2 6 7 lda [dp]+y d7 2 6 8 lda {x} d4 1 3 9 lda {x}+ db 1 4 x-register auto-increment : a ? (m), x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : (m) ? imm - - - - - - - - 11 ldx #imm 1e 2 2 load x-register n - - - - - z - 12 ldx dp cc 2 3 x ? (m) 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load x-register n - - - - - z - 16 ldy dp c9 2 3 y ? (m) 17 ldy dp + y d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 3 store accumulator contents in memory - - - - - - - - 20 sta dp + x e6 2 4 (m) ? a 21 sta !abs e7 3 4 22 sta !abs + y f5 3 5 23 sta [dp + x] f6 2 6 24 sta [dp] + y f7 2 6 25 sta {x} f4 1 3 26 sta {x}+ fb 1 4 x-register auto-increment : (m) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory - - - - - - - - 28 stx dp + y ed 2 5 (m) ? x 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory - - - - - - - - 31 sty dp + x f9 2 5 (m) ? y 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n - - - - - z - 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n - - - - - z - 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n - - - - - z - 36 txa c8 1 2 transfer x-register contents to accumulator : a ? x n - - - - - z - 37 txsp 8e 1 2 transfer x-register contents to stack-pointer : sp ? x n - - - - - z - 38 tya bf 1 2 transfer y-register contents to accumulator : a ? y n - - - - - z - 39 xax ee 1 4 exchange x-register contents with accumulator : x ? a - - - - - - - - 40 xay de 1 4 exchange y-register contents with accumulator : y ? a - - - - - - - - 41 xma dp bc 2 5 exchange memory contents with accumulator n - - - - - z - 42 xma dp + x ad 2 6 (m) ? a 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y - - - - - - - -
gms81508b/16b/24b, gms82512/16/24 xviii may. 2001 ver 2.0 16-bit operation bit manipulation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry : ya ? ya + (dp+1)(dp) nv - - h - zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : n - - - - - zc ya - (dp+1)(dp) 3 decw dp bd 2 6 decrement memory pair : (dp+1)(dp) ? {(dp+1)(dp)} - 1 n - - - - - z - 4 incw dp 9d 2 6 increment memory pair : (dp+1)(dp) ? {(dp+1)(dp)} + 1 n - - - - - z - 5 ldya dp 7d 2 5 load ya : ya ? (dp+1)(dp) n - - - - - z - 6 stya dp dd 2 5 store ya : (dp+1)(dp) ? ya - - - - - - - - 7 subw dp 3d 2 5 16-bits subtract without carry : ya ? ya - (dp+1)(dp) nv - - h - zc no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? c (m.bit) - - - - - - - c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? c (m.bit) - - - - - - - c 3 bit dp 0c 2 4 bit test a with memory : mm - - - - z - 4 bit !abs 1c 3 5 z ? a m, n ? (m 7 ), v ? (m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : (m.bit) ? 0 - - - - - - - - 6 clr1a a.bit 2b 2 2 clear a.bit : (a.bit) ? 0 - - - - - - - - 7 clrc 20 1 2 clear c-flag : c ? 0 - - - - - - - 0 8 clrg 40 1 2 clear g-flag : g ? 0 - - 0 - - - - - 9 clrv 80 1 2 clear v-flag : v ? 0 - 0 - - 0 - - - 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? c ? (m.bit) - - - - - - - c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? c ? (m.bit) - - - - - - - c 12 ldc m.bit cb 3 4 load c-flag : c ? (m.bit) - - - - - - - c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? (m.bit) - - - - - - - c 14 not1 m.bit 4b 3 5 bit complement : (m.bit) ? (m.bit) - - - - - - - - 15 or1 m.bit 6b 3 5 bit or c-flag : c ? c v (m.bit) - - - - - - - c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? c v (m.bit) - - - - - - - c 17 set1 dp.bit x1 2 4 set bit : (m.bit) ? 1 - - - - - - - - 18 seta1 a.bit 0b 2 2 set a.bit : (a.bit) ? 1 - - - - - - - - 19 setc a0 1 2 set c-flag : c ? 1 - - - - - - - 1 20 setg c0 1 2 set g-flag : g ? 1 - - 1 - - - - - 21 stc m.bit eb 3 6 store c-flag : (m.bit) ? c - - - - - - - - 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - (m), (m) ? (m) (a) n - - - - - z - 23 tset1 !abs 3c 3 6 test and set bits with a : a - (m), (m) ? (m) v (a) n - - - - - z -
gms81508b/16b/24b, gms82512/16/24 may. 2001 ver 2.0 xix branch / jump operation no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : - - - - - - - - 2 bbc dp.bit,rel y3 3 5/7 if(bit) = 0, then pc ? pc + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit clear : - - - - - - - - 4 bbs dp.bit,rel x3 3 5/7 if(bit) = 1, then pc ? pc + rel 5 bcc rel 50 2 2/4 branch if carry bit clear : if(c) = 0, then pc ? pc + rel mm - - - - z - 6 bcs rel d0 2 2/4 branch if carry bit set : if (c) =1, then pc ? pc + rel - - - - - - - - 7 beq rel f0 2 2/4 branch if equal : if (z) = 1, then pc ? pc + rel - - - - - - - - 8 bmi rel 90 2 2/4 branch if minus : if (n) = 1, then pc ? pc + rel - - - - - - - - 9 bne rel 70 2 2/4 branch if not equal : if (z) = 0, then pc ? pc + rel - - - - - - - - 10 bpl rel 10 2 2/4 branch if not minus : if (n) = 0, then pc ? pc + rel - - - - - - - - 11 bra rel 2f 2 4 branch always : pc ? pc + rel - - - - - - - - 12 bvc rel 30 2 2/4 branch if overflow bit clear : - - - - - - - - if (v) = 0, then pc ? pc + rel 13 bvs rel b0 2 2/4 branch if overflow bit set : - - - - - - - - if (v) = 1, then pc ? pc + rel 14 call !abs 3b 3 8 subroutine call - - - - - - - - 15 call [dp] 5f 2 8 m(sp) ? (pc h ), sp ? sp-1, m(sp) ? (pc l ), sp ? sp-1 if !abs, pc ? abs ; if [dp], pc l ? (dp), pc h ? (dp+1) 16 cbne dp,rel fd 3 5/7 compare and branch if not equal ; - - - - - - - - 17 cbne dp + x, rel 8d 3 6/8 if a 1 (m), then pc ? pc + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : - - - - - - - - 19 dbne y,rel 7b 2 4/6 if (m) 1 0, then pc ? pc + rel. 20 jmp !abs 1b 3 3 unconditional jump - - - - - - - - 21 jmp [!abs] 1f 3 5 pc ? jump address 22 jmp [dp] 3f 2 4 23 pcall 4f 2 6 u-page call : m(sp) ? (pc h ), sp ? sp -1, - - - - - - - - m(sp) ? (pc l ), sp ? sp -1, pc l ? (upage), pc h ? "off h " 24 tcall n na 1 8 table call : - - - - - - - - m(sp) ? (pc h ), sp ? sp -1, m(sp) ? (pc l ), sp ? sp -1 pc l ? (table vector l), pc h ? (table vector h)
gms81508b/16b/24b, gms82512/16/24 xx may. 2001 ver 2.0 control operation & etc. no. mnenonic op code byte no. cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt: - - - 1 - 0 - - b ? 1, m(sp) ? (pc h ), sp ? sp - 1, m(s) ? (pc l ), sp ? s - 1, m(sp) ? psw, sp ? sp - 1, pc l ? (0ffde h ), pc h ? (0ffdf h ) 2 di 60 1 3 disable interrupts : i ? 0 - - - - - 0 - - 3 ei e0 1 3 enable interrupts : i ? 1 - - - - - 1 - - 4 nop ff 1 2 no operation - - - - - - - - 5 pop a 0d 1 4 pop from stack - - - - - - - - 6 pop x 2d 1 4 sp ? sp + 1, reg. ? m(sp) 7 pop y 4d 1 4 8 pop psw 6d 1 4 (restored) 9 push a 0e 1 4 push to stack - - - - - - - - 10 push x 2e 1 4 m(sp) ? reg. sp ? sp - 1 11 push y 4e 1 4 12 push psw 6e 1 4 13 ret 6f 1 5 return from subroutine : - - - - - - - - sp ? sp+1, pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 14 reti 7f 1 6 return from interrupt : (restored) sp ? sp+1, psw ? m(sp), sp ? sp+1,pc l ? m(sp), sp ? sp+1, pc h ? m(sp) 15 stop ef 1 3 stop mode (halt cpu, stop oscillator) - - - - - - - -
d. mask order sheet mask order & verification sheet gms81508b 1. customer information company name application order date yyyy tel: fax: name & signature: .o tp file data file name (please check mark ? into ) customer should write inside thick line box. 64lqfp 64sdip 64mqfp ( ) .otp 3.0v yyww korea gms815xxb-hf customers logo chollian internet hitel package 24k 8k 16k rom size (bytes) mask data check sum ( ) 2. device information pfd option 2.4v not use mm dd 2000 h (24k) 4000 h (16k) 6000 h (8k) 7fff h 3. marking specification customer logo is not required. yyww korea gms815xxb-hf hynix customers part number if the customer logo must be used in the special mark, please submit a clean original of the logo. 4. delivery schedule date quantity hynix confirmation yyyy mm dd yyyy mm dd customer sample risk order pcs pcs e-mail address: 5. rom code verification yyyy mm dd verification date: please confirm out verification data. check sum: tel: fax: name & signature: e-mail address: yyyy mm dd approval date: i agree with your verification data and confirm you to make mask set. tel: fax: name & signature: e-mail address: 08 or 16 or 24 set ff h in blanked area -hf gms81516b gms81524b may, 01. 2001
mask order & verification sheet gms82512 1. customer information company name application order date yyyy tel: fax: name & signature: .o tp file data file name (please check mark ? into ) customer should write inside thick line box. 42sdip 44mqfp ( ) .otp 3.0v yyww korea gms825xx-hh customers logo chollian internet hitel package 24k 12k 16k rom size (bytes) mask data check sum ( ) 2. device information pfd option 2.4v not use mm dd 2000 h (24k) 4000 h (16k) 5000 h (12k) 7fff h 3. marking specification customer logo is not required. yyww korea gms825xx-hh hynix customers part number if the customer logo must be used in the special mark, please submit a clean original of the logo. 4. delivery schedule date quantity hynix confirmation yyyy mm dd yyyy mm dd customer sample risk order pcs pcs e-mail address: 5. rom code verification yyyy mm dd verification date: please confirm out verification data. check sum: tel: fax: name & signature: e-mail address: yyyy mm dd approval date: i agree with your verification data and confirm you to make mask set. tel: fax: name & signature: e-mail address: 08 or 16 or 24 set ff h in blanked area -hh gms82516 gms82524 may, 01. 2001

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